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We want to keep the tri-state buffers located between the FPGA and the board, in 'Z' state until we launch an i2c connection. We launch an i2c start condition, make the SCL direction 'OUT' to start the i2c protocol and at the end of the i2c connection at the stop condition, we re-make the tri-state buffers at 'Z' state. Change-Id: Ic597a70d0427832547f6b539864c24ce20a18c64 Signed-off-by: Ahmed BOUDJELIDA <aboudjelida@nanoxplore.com> Reviewed-on: https://review.openocd.org/c/openocd/+/7989 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> |
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# SPDX-License-Identifier: BSD-3-Clause
# Copyright (C) 2023 by NanoXplore, France - all rights reserved
This is the source code of Nanoxplore USB-JTAG Adapter Angie's bitstream.
This bitstream is for the "xc6slx9-2tqg144" Spartan-6 Xilinx FPGA.
To generate this bitstream, you need to install Xilinx ISE Webpack 14.7
You will need to give the ISE software path : export XILINX_HOME=path/to/ise/sw
Please set the enviromnent first by executing the ". ./set_env.sh"
All you have to do now is to write your vhd and constrains codes.
One all is setup, you can use the make commands:
make compile : to compile your (.vhd & .ucf) files in the "src" directory
A directory named "build" will be created, which contains all the generated
files including the bitstream file.
make clean : to delete the build directory.