mirror of
https://git.code.sf.net/p/openocd/code
synced 2024-11-22 10:46:27 +00:00
aee495e785
add new i2c bit-banging feature, we can now connect in JTAG with the SoC target and in i2c with the main board components at the same time. Change-Id: I8e4516fe1ad5238e0373444f1c3c9bc0814d0f52 Signed-off-by: Ahmed BOUDJELIDA <aboudjelida@nanoxplore.com> Reviewed-on: https://review.openocd.org/c/openocd/+/7796 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
110 lines
3.6 KiB
Makefile
110 lines
3.6 KiB
Makefile
# SPDX-License-Identifier: BSD-3-Clause
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# Copyright (C) 2023 by NanoXplore, France - all rights reserved
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# Needed by timing test
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export PROJECT := angie_bitstream
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TARGET_PART := xc6slx9-2tqg144
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export TOPLEVEL := S609
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# Detects the ROOT dir from the .git marker
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sp :=
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sp +=
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_walk = $(if $1,$(wildcard /$(subst $(sp),/,$1)/$2) $(call _walk,$(wordlist 2,$(words $1),x $1),$2))
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_find = $(firstword $(call _walk,$(strip $(subst /, ,$1)),$2))
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_ROOT := $(patsubst %/.git,%,$(call _find,$(CURDIR),.git))
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SHELL := /bin/bash
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TOP_DIR := $(realpath $(_ROOT))
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HDL_DIR := $(CURDIR)
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SRC_DIR := $(HDL_DIR)/src
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TOOLS_DIR := $(TOP_DIR)/tools/build
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COMMON_DIR := $(TOP_DIR)/common/hdl
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COMMON_HDL_DIR := $(COMMON_DIR)/src
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COMMON_LIBS := $(COMMON_DIR)/libs
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HDL_BUILD_DIR := $(HDL_DIR)/build
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OUTPUT_DIR ?= $(HDL_BUILD_DIR)/output
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FINAL_OUTPUT_DIR := $(OUTPUT_DIR)/$(PROJECT)
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# Tools
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MKDIR := mkdir -p
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CP := cp -f
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HDL_SRC_PATH := $(addprefix $(COMMON_DIR)/ips/, $(HDL_IPS)) $(HDL_DIR)
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VHDSOURCE += $(foreach ip,$(HDL_SRC_PATH),$(wildcard $(ip)/src/*.vhd))
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VSOURCE += $(foreach ip,$(HDL_SRC_PATH),$(wildcard $(ip)/src/*.v))
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VSOURCE += $(foreach ip,$(HDL_SRC_PATH),$(wildcard $(ip)/src/*.vh))
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CONSTRAINTS ?= $(SRC_DIR)/$(PROJECT).ucf
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COMMON_OPTS := -intstyle xflow
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XST_OPTS :=
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NGDBUILD_OPTS :=
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MAP_OPTS := -mt 2
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PAR_OPTS := -mt 4
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BITGEN_OPTS := -g Binary:Yes
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XILINX_PLATFORM := lin64
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PATH := $(PATH):$(XILINX_HOME)/bin/$(XILINX_PLATFORM)
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RUN = @echo -ne "\n\n\e[1;33m======== $(1) ========\e[m\n\n"; \
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cd $(HDL_BUILD_DIR) && $(XILINX_HOME)/bin/$(XILINX_PLATFORM)/$(1)
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compile: $(HDL_BUILD_DIR)/$(PROJECT).bin
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install: $(HDL_BUILD_DIR)/$(PROJECT).bin
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$(MKDIR) $(FINAL_OUTPUT_DIR)
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$(CP) $(HDL_BUILD_DIR)/$(PROJECT).bin $(FINAL_OUTPUT_DIR)
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clean:
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rm -rf $(HDL_BUILD_DIR)
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$(HDL_BUILD_DIR)/$(PROJECT).bin: $(HDL_BUILD_DIR)/$(PROJECT).ncd
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$(call RUN,bitgen) $(COMMON_OPTS) $(BITGEN_OPTS) \
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-w $(PROJECT).ncd $(PROJECT).bit
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$(HDL_BUILD_DIR)/$(PROJECT).ncd: $(HDL_BUILD_DIR)/$(PROJECT).map.ncd
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$(call RUN,par) $(COMMON_OPTS) $(PAR_OPTS) \
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-w $(PROJECT).map.ncd $(PROJECT).ncd $(PROJECT).pcf
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$(HDL_BUILD_DIR)/$(PROJECT).map.ncd: $(HDL_BUILD_DIR)/$(PROJECT).ngd
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$(call RUN,map) $(COMMON_OPTS) $(MAP_OPTS) \
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-p $(TARGET_PART) \
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-w $(PROJECT).ngd -o $(PROJECT).map.ncd $(PROJECT).pcf
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$(HDL_BUILD_DIR)/$(PROJECT).ngd: $(HDL_BUILD_DIR)/$(PROJECT).ngc
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$(call RUN,ngdbuild) $(COMMON_OPTS) $(NGDBUILD_OPTS) \
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-p $(TARGET_PART) -uc $(CONSTRAINTS) \
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$(PROJECT).ngc $(PROJECT).ngd
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$(HDL_BUILD_DIR)/$(PROJECT).ngc: $(HDL_BUILD_DIR)/$(PROJECT).prj $(HDL_BUILD_DIR)/$(PROJECT).scr
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$(call RUN,xst) $(COMMON_OPTS) -ifn $(PROJECT).scr
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$(HDL_BUILD_DIR)/$(PROJECT).scr: | $(HDL_BUILD_DIR)
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@echo "Updating $@"
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@mkdir -p $(HDL_BUILD_DIR)
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@rm -f $@
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@echo "run" \
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"-ifn $(PROJECT).prj" \
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"-ofn $(PROJECT).ngc" \
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"-ifmt mixed" \
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"$(XST_OPTS)" \
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"-top $(TOPLEVEL)" \
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"-ofmt NGC" \
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"-p $(TARGET_PART)" \
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> $(HDL_BUILD_DIR)/$(PROJECT).scr
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$(HDL_BUILD_DIR)/$(PROJECT).prj: | $(HDL_BUILD_DIR)
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@echo "Updating $@"
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@rm -f $@
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@$(foreach file,$(VSOURCE),echo "verilog work \"$(file)\"" >> $@;)
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@$(foreach file,$(VHDSOURCE),echo "vhdl work \"$(file)\"" >> $@;)
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@$(foreach lib,$(HDL_LIBS),$(foreach file,$(wildcard $(COMMON_LIBS)/$(lib)/src/*.vhd),echo "vhdl $(lib) \"$(file)\"" >> $@;))
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@$(foreach lib,$(HDL_LIBS),$(foreach file,$(wildcard $(COMMON_LIBS)/$(lib)/src/*.v),echo "verilog $(lib) \"$(file)\"" >> $@;))
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@$(foreach lib,$(HDL_LIBS),$(foreach file,$(wildcard $(COMMON_LIBS)/$(lib)/src/*.vh),echo "verilog $(lib) \"$(file)\"" >> $@;))
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$(HDL_BUILD_DIR):
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$(MKDIR) $(HDL_BUILD_DIR)
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.PHONY: clean compile install
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