Shiji Yang de0c143742 ramips: mt762{0,8}: reduce default MMC clock to 24 MHz ...

The upstream mtk-sd driver did not perform specific timing
optimization for MT762x series SoC, hence the SDHC peripheral
of some boards cannot run at too high frequency. Reduce the
maximum clock frequency to fix the mmc read/write error.

Closes: https://github.com/openwrt/openwrt/issues/17364
Signed-off-by: Shiji Yang <yangshiji66@qq.com>
Link: https://github.com/openwrt/openwrt/pull/17375
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>

2024-12-26 15:23:49 +01:00

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