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1679dcddfa
The EN751221 SPI controller requires quiet time between operations otherwise NAND writes are often (almost always) not committed. udelay(100) works but does not account for the SPI clock speed which is configurable. This issue has been observed on two different SoCs with different brands of SPI NAND. The vendor code sets the CS state twice in order to add one SPI op worth of quiet time before and after each operation, this seems like a good strategy and is in any case well tested. Signed-off-by: Caleb James DeLisle <cjd@cjdns.fr>
30 lines
725 B
Diff
30 lines
725 B
Diff
--- a/drivers/spi/Kconfig
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+++ b/drivers/spi/Kconfig
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@@ -355,7 +355,7 @@ config SPI_DLN2
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config SPI_AIROHA_EN7523
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bool "Airoha EN7523 SPI controller support"
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- depends on ARCH_AIROHA
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+ depends on ARCH_AIROHA || ECONET_EN75
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help
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This enables SPI controller support for the Airoha EN7523 SoC.
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--- a/drivers/spi/spi-en7523.c
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+++ b/drivers/spi/spi-en7523.c
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@@ -82,10 +82,11 @@ static void opfifo_write(u32 cmd, u32 le
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static void set_cs(int state)
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{
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- if (state)
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- opfifo_write(OP_CSH, 1);
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- else
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- opfifo_write(OP_CSL, 1);
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+ u32 cmd = state ? OP_CSH : OP_CSL;
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+
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+ /* EN751221 drops writes if we don't send this twice. */
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+ opfifo_write(cmd, 1);
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+ opfifo_write(cmd, 1);
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}
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static void manual_begin_cmd(void)
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