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The EN751221 SPI controller requires quiet time between operations otherwise NAND writes are often (almost always) not committed. udelay(100) works but does not account for the SPI clock speed which is configurable. This issue has been observed on two different SoCs with different brands of SPI NAND. The vendor code sets the CS state twice in order to add one SPI op worth of quiet time before and after each operation, this seems like a good strategy and is in any case well tested. Signed-off-by: Caleb James DeLisle <cjd@cjdns.fr>