WDMA + WED #3

New Issue

Sirherobrine23 · 2025-11-08T01:36:34Z

Sirherobrine23 commented

2025-11-08 01:36:34 +00:00

gpl_tplink-xx230v/sdk/en7529/linux-4.4.115/arch/arm/boot/dts/en7523.dts Lines 230 to 267 in 4d76b59039

 	wdma{
     compatible = "en751221,wdma";
     reg = <0x1fa06000 0x400 >,
      			<0x1fa06400 0x400 >;
     interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
       					 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
         				 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
         				 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
         				 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
         				 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
   };
   wed{
     compatible = "en751221,wed";
     wed_num = <2>;
     pci_slot_map = <0>, <1>;
     reg = <0x1fa02000 0xb00 >,
      			<0x1fa03000 0xb00 >;
     interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
      						 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
   };
   wed2{
     compatible = "en751221,wed2";
     wed_num = <2>;
     pci_slot_map = <0>, <1>;
     reg = <0x1fa02000 0xb00 >,
      			<0x1fa03000 0xb00 >;
     interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
        					 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
   };
   wed_test{
     compatible = "en751221,wed_test";
     wed_num = <2>;
     reg = <0x1fa02b00 0x100 >,
      			<0x1fa03b00 0x100 >;
   };

IRQs:

		gpl_tplink-xx230v/sdk/en7529/linux-4.4.115/arch/mips/econet/irq.c
		Lines 172 to 179 in 4d76b59039
	
				    {cpu0,  WOE0_INTR-1,        GIC_POL_POS,    GIC_TRIG_LEVEL, GIC_FLAG_IPI, IRQ_NAME_WOE0},   /*    51     WIFI Offload Engine 0 */

				    {cpu0,  WOE1_INTR-1,        GIC_POL_POS,    GIC_TRIG_LEVEL, GIC_FLAG_IPI, IRQ_NAME_WOE1},   /*    52     WIFI Offload Engine 1 */

				    {cpu0,  WDMA0_P0_INTR-1,    GIC_POL_POS,    GIC_TRIG_LEVEL, GIC_FLAG_IPI, IRQ_NAME_WDMA0_P0},/*   53     WIFI DMA 0 port 0 */

				    {cpu0,  WDMA0_P1_INTR-1,    GIC_POL_POS,    GIC_TRIG_LEVEL, GIC_FLAG_IPI, IRQ_NAME_WDMA0_P1},/*   54     WIFI DMA 0 port 1 */

				    {cpu0,  WDMA0_WOE_INTR-1,   GIC_POL_POS,    GIC_TRIG_LEVEL, GIC_FLAG_IPI, IRQ_NAME_WDMA0_WOE},/*  55     WIFI DMA 0 for WOE */

				    {cpu0,  WDMA1_P0_INTR-1,    GIC_POL_POS,    GIC_TRIG_LEVEL, GIC_FLAG_IPI, IRQ_NAME_WDMA1_P0},/*   56     WIFI DMA 1 port 0 */

				    {cpu0,  WDMA1_P1_INTR-1,    GIC_POL_POS,    GIC_TRIG_LEVEL, GIC_FLAG_IPI, IRQ_NAME_WDMA1_P1},/*   56     WIFI DMA 1 port 1 */

				    {cpu0,  WDMA1_WOE_INTR-1,   GIC_POL_POS,    GIC_TRIG_LEVEL, GIC_FLAG_IPI, IRQ_NAME_WDMA1_WOE},/*  58     WIFI DMA 1 for WOE */

		gpl_tplink-xx230v/sdk/en7529/linux-4.4.115/arch/mips/include/asm/tc3162/tc3182_int_source.h
		Lines 37 to 44 in 4d76b59039
	
				    WDMA1_WOE_INTR, /*  12      58      WIFI DMA 1 for WOE */

				    WDMA1_P1_INTR,  /*  13      57      WIFI DMA 1 port 1 */

				    WDMA1_P0_INTR,  /*  14      56      WIFI DMA 1 port 0 */

				    WDMA0_WOE_INTR, /*  15      55      WIFI DMA 1 for WOE */

				    WDMA0_P1_INTR,  /*  16      54      WIFI DMA 1 port 1 */

				    WDMA0_P0_INTR,  /*  17      53      WIFI DMA 1 port 0 */

				    WOE1_INTR,      /*  18      52      WIFI Offload Engine 1 */

				    WOE0_INTR,      /*  19      51      WIFI Offload Engine 0 */

https://sirherobrine23.com.br/tplink_xx230v/gpl_tplink-xx230v/src/commit/4d76b590398d1e510a2a893f6fc4c69bfedb5768/sdk/en7529/linux-4.4.115/arch/arm/boot/dts/en7523.dts#L230-L267 ---- ## IRQs: - https://sirherobrine23.com.br/tplink_xx230v/gpl_tplink-xx230v/src/commit/4d76b590398d1e510a2a893f6fc4c69bfedb5768/sdk/en7529/linux-4.4.115/arch/mips/econet/irq.c#L172-L179 - https://sirherobrine23.com.br/tplink_xx230v/gpl_tplink-xx230v/src/commit/4d76b590398d1e510a2a893f6fc4c69bfedb5768/sdk/en7529/linux-4.4.115/arch/mips/include/asm/tc3162/tc3182_int_source.h#L37-L44

merbanan commented

2025-11-08 12:06:22 +00:00

The WED and WDMA hardware blocks are probably inherited from the EN7528 SoC design. It seems like they took the mips irq indices and mapped them in with an offset of 16.

The wed is supposed to only be able to accelerate in the downstream direction. The NPUs are supposed to be able to do both US/DS. The NPUs are most likely driver dependant.

If the aim is long term linux mainline support then I think the WED path should be taken instead of the NPUs. On the AN7581 the NPUs are standard RISCV32 and in theory one could implement open source packet offloading there. The AN7523 NPU binaries are some kind of obfuscation. Most likely the opcodes are substituted or something.

Anyway wed enabled driver code should be possible to get going as it should be similar to what Mediatek has in main line.

The WED and WDMA hardware blocks are probably inherited from the EN7528 SoC design. It seems like they took the mips irq indices and mapped them in with an offset of 16. The wed is supposed to only be able to accelerate in the downstream direction. The NPUs are supposed to be able to do both US/DS. The NPUs are most likely driver dependant. If the aim is long term linux mainline support then I think the WED path should be taken instead of the NPUs. On the AN7581 the NPUs are standard RISCV32 and in theory one could implement open source packet offloading there. The AN7523 NPU binaries are some kind of obfuscation. Most likely the opcodes are substituted or something. Anyway wed enabled driver code should be possible to get going as it should be similar to what Mediatek has in main line.

Sirherobrine23 commented

2025-11-08 12:24:54 +00:00

I haven't found any reference drivers in Econet's GPLs so far. I'm going to download them to my computer so I can search better. I found almost nothing in the GPL I have from Airoha.

When I was testing the Mediatek drivers, I couldn't get any signal that was working.

I haven't found any reference drivers in Econet's GPLs so far. I'm going to download them to my computer so I can search better. I found almost nothing in the GPL I have from Airoha. When I was testing the Mediatek drivers, I couldn't get any signal that was working.

merbanan commented

2025-11-08 13:01:30 +00:00

I dont think this hit production devices besides for EN7528. And you need to understand alot about the mt76 to be able to get it working properly. The wed/wdma is from the same generation as MT7622 so maybe it is needed to look back at that platform and its open code to see if the old integration code worked better.

merbanan commented

2025-11-08 13:20:32 +00:00

Ok, it looks like the WED is connected to GDM3. So that is how packets come in to the PPE(Frame engine). The frame engine needs proper setup to handle the packets.