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Ethernet #2

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opened 2025-11-08 00:44:45 +00:00 by Sirherobrine23 · 22 comments
Sirherobrine23 commented 2025-11-08 00:44:45 +00:00
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gpl_tplink-xx230v/sdk/en7529/linux-4.4.115/arch/arm/boot/dts/en7523.dts Lines 348 to 363 in 4d76b59039
frame_engine: frame_engine@1fb50000 {
compatible = "econet,ecnt-frame_engine";
reg = <0x1fb50000 0x2600>, //FE + PPE
<0x1fb54000 0x4000>, //QDMA
<0x1fb58000 0x8000>; //SWITCH
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, // QDMA LAN INT1 21+16
<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, // QDMA LAN INT2 39+16
<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, // QDMA LAN INT3 40+16
<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, // QDMA LAN INT4 41+16
<GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, // QDMA WAN INT1 22+16
<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, // QDMA WAN INT2 42+16
<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, // QDMA WAN INT3 43+16
<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, // QDMA WAN INT4 44+16
<GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, // FE ERROR INTR 33+16
<GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; // PDMA INTR 48+16
};

gpl_tplink-xx230v/sdk/en7529/linux-4.4.115/arch/arm/boot/dts/en7523.dts Lines 298 to 304 in 4d76b59039
xsi@1fa60000 {
compatible = "econet,ecnt-xsi";
reg = <0x1fa60000 0x300>, //hsgmii ae
<0x1fa70000 0x300>, //hsgmii pcie0
<0x1fa71000 0x300>, //hsgmii pcie1
<0x1fa80000 0x300>; //hsgmii usb
};

Files

qdma_dev consume

gpl_tplink-xx230v/sdk/en7529/linux-4.4.115/qdma_dev.i Lines 62496 to 62506 in 4d76b59039
static int __inline__ __attribute__((always_inline)) __attribute__((no_instrument_function)) qdmaChecConfigDone(uint reg, uint doneBit)
{
int RETRY = 3 ;
volatile uint regValue = 0 ;
while(RETRY--) {
regValue = get_frame_engine_data(reg) ;
if(regValue & doneBit) {
break ;
}

External comments

XPON - Related but will not be implemention now

gpl_tplink-xx230v/sdk/en7529/linux-4.4.115/arch/arm/boot/dts/en7523.dts Lines 406 to 413 in 4d76b59039
pon_phy: pon_phy@1faf0000 {
compatible = "econet,ecnt-pon_phy";
reg = <0x1faf0000 0x800>, // PON_PHY_ASIC_RG range
<0x1fa2ff24 0x4>, // PON_PHY_FPGA_RG_TX_OFF
<0x1faf3000 0xfff>, // PON_PHY_ASIC_RG range2
<0x1faf4000 0xfff>; // PON_PHY_ASIC_RG range3
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; // XPON_PHY_INTR 27+16
};

gpl_tplink-xx230v/sdk/en7529/linux-4.4.115/arch/arm/boot/dts/en7523.dts Lines 391 to 397 in 4d76b59039
xpon_mac: xpon@1fb64000 {
compatible = "econet,ecnt-xpon";
reg = <0x1fb64000 0x3e8>,
<0x1fb66000 0x23c>;
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, // XPON MAC INT 26+16
<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;// DYINGGASP INT 18+16
};

https://sirherobrine23.com.br/tplink_xx230v/gpl_tplink-xx230v/src/commit/4d76b590398d1e510a2a893f6fc4c69bfedb5768/sdk/en7529/linux-4.4.115/arch/arm/boot/dts/en7523.dts#L348-L363 https://sirherobrine23.com.br/tplink_xx230v/gpl_tplink-xx230v/src/commit/4d76b590398d1e510a2a893f6fc4c69bfedb5768/sdk/en7529/linux-4.4.115/arch/arm/boot/dts/en7523.dts#L298-L304 --- ## Files - https://sirherobrine23.com.br/tplink_xx230v/gpl_tplink-xx230v/src/commit/4d76b590398d1e510a2a893f6fc4c69bfedb5768/sdk/en7529/linux-4.4.115/arch/arm/mach-econet/ecnt_frame_engine.c - https://sirherobrine23.com.br/tplink_xx230v/gpl_tplink-xx230v/src/commit/4d76b590398d1e510a2a893f6fc4c69bfedb5768/sdk/en7529/linux-4.4.115/arch/arm/mach-econet/ecnt_xsi.c ### qdma_dev consume https://sirherobrine23.com.br/tplink_xx230v/gpl_tplink-xx230v/src/commit/4d76b590398d1e510a2a893f6fc4c69bfedb5768/sdk/en7529/linux-4.4.115/qdma_dev.i#L62496-L65608 ## External comments - https://github.com/openwrt/openwrt/pull/20104#issuecomment-3467331940 - https://github.com/openwrt/openwrt/pull/20104#issuecomment-3467506602 - https://github.com/openwrt/openwrt/pull/20104#issuecomment-3467552634 ---- ## XPON - Related but will not be implemention now - https://sirherobrine23.com.br/tplink_xx230v/gpl_tplink-xx230v/src/commit/4d76b590398d1e510a2a893f6fc4c69bfedb5768/sdk/en7529/linux-4.4.115/arch/arm/mach-econet/ecnt_xpon.c - https://sirherobrine23.com.br/tplink_xx230v/gpl_tplink-xx230v/src/commit/4d76b590398d1e510a2a893f6fc4c69bfedb5768/sdk/en7529/linux-4.4.115/arch/arm/mach-econet/ecnt_pon_phy.c https://sirherobrine23.com.br/tplink_xx230v/gpl_tplink-xx230v/src/commit/4d76b590398d1e510a2a893f6fc4c69bfedb5768/sdk/en7529/linux-4.4.115/arch/arm/boot/dts/en7523.dts#L406-L413 https://sirherobrine23.com.br/tplink_xx230v/gpl_tplink-xx230v/src/commit/4d76b590398d1e510a2a893f6fc4c69bfedb5768/sdk/en7529/linux-4.4.115/arch/arm/boot/dts/en7523.dts#L391-L397
Sirherobrine23 added a new dependency 2025-11-08 13:21:59 +00:00
#3 WDMA + WED
merbanan commented 2025-11-08 13:25:00 +00:00
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I am getting packet data through to the CPU now. But it is not correctly mapped to the correct interface. I am seeing ARP and stuff.

I am getting packet data through to the CPU now. But it is not correctly mapped to the correct interface. I am seeing ARP and stuff.
merbanan commented 2025-11-08 19:32:34 +00:00
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00:02:48.104438 IP 192.168.1.100 > OpenWrt.lan: ICMP echo request, id 139, seq 5, length 64
00:02:48.104561 IP OpenWrt.lan > 192.168.1.100: ICMP echo reply, id 139, seq 5, length 64
00:02:49.128439 IP 192.168.1.100 > OpenWrt.lan: ICMP echo request, id 139, seq 6, length 64
00:02:49.128562 IP OpenWrt.lan > 192.168.1.100: ICMP echo reply, id 139, seq 6, length 64
00:02:50.152444 IP 192.168.1.100 > OpenWrt.lan: ICMP echo request, id 139, seq 7, length 64
00:02:50.152568 IP OpenWrt.lan > 192.168.1.100: ICMP echo reply, id 139, seq 7, length 64

EN7523 CPU can now RX

00:02:48.104438 IP 192.168.1.100 > OpenWrt.lan: ICMP echo request, id 139, seq 5, length 64 00:02:48.104561 IP OpenWrt.lan > 192.168.1.100: ICMP echo reply, id 139, seq 5, length 64 00:02:49.128439 IP 192.168.1.100 > OpenWrt.lan: ICMP echo request, id 139, seq 6, length 64 00:02:49.128562 IP OpenWrt.lan > 192.168.1.100: ICMP echo reply, id 139, seq 6, length 64 00:02:50.152444 IP 192.168.1.100 > OpenWrt.lan: ICMP echo request, id 139, seq 7, length 64 00:02:50.152568 IP OpenWrt.lan > 192.168.1.100: ICMP echo reply, id 139, seq 7, length 64 EN7523 CPU can now RX
Sirherobrine23 commented 2025-11-08 19:35:49 +00:00
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You can send me the patcher so I can test it when I receive the xx230v.

You can send me the patcher so I can test it when I receive the xx230v.
merbanan commented 2025-11-08 19:37:18 +00:00
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Yeah, I will. I'll try to sort out tx now.

Yeah, I will. I'll try to sort out tx now.
Sirherobrine23 added the Kind/Testing
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 labels 2025-11-09 01:29:56 +00:00
Sirherobrine23 added this to the EN7523 project 2025-11-09 01:32:22 +00:00
Sirherobrine23 moved this to In Progress in EN7523 on 2025-11-09 01:33:06 +00:00
Sirherobrine23 commented 2025-11-09 19:45:39 +00:00
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gpl_tplink-xx230v/sdk/en7529/linux-4.4.115/arch/arm/boot/dts/en7523.dts Line 295 in 4d76b59039
reg = <0x1fb30000 0x2b0>;

openwrt/target/linux/airoha/dts/en7523.dtsi Line 398 in b8dc284d66
<0x1fb30000 0x1000>;

Why are the values different?

https://sirherobrine23.com.br/tplink_xx230v/gpl_tplink-xx230v/src/commit/4d76b590398d1e510a2a893f6fc4c69bfedb5768/sdk/en7529/linux-4.4.115/arch/arm/boot/dts/en7523.dts#L295 https://sirherobrine23.com.br/tplink_xx230v/openwrt/src/commit/b8dc284d6687654b58be303c51135a40aa0c5764/target/linux/airoha/dts/en7523.dtsi#L398 Why are the values different?
merbanan commented 2025-11-09 19:50:58 +00:00
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I fucked up I think.

I fucked up I think.
merbanan commented 2025-11-09 19:55:21 +00:00
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gdump@1fbf9000 {
	compatible = "econet,ecnt-gdump";
	reg = <0x1fbf9000 0x84>;	
};
gdump@1fbf9000 { compatible = "econet,ecnt-gdump"; reg = <0x1fbf9000 0x84>; };
merbanan commented 2025-11-09 19:57:46 +00:00
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Lovely, I was getting hangs after 100s of packets. This setting assigns sram over to the fe block. So I guess it get upset because of that.

Lovely, I was getting hangs after 100s of packets. This setting assigns sram over to the fe block. So I guess it get upset because of that.
Sirherobrine23 added reference airoha_en7523_eth 2025-11-09 19:57:48 +00:00
merbanan commented 2025-11-09 20:00:04 +00:00
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devmem 0x1fbf9074 that needs to be 3.

devmem 0x1fbf9074 that needs to be 3.
merbanan commented 2025-11-09 20:10:20 +00:00
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Ok, still hangs after a while. Probably has to do with the descriptor allocation/queues.

Ok, still hangs after a while. Probably has to do with the descriptor allocation/queues.
merbanan commented 2025-11-09 20:22:22 +00:00
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Ok, 74 -> 0x74 is probably needed.

Ok, 74 -> 0x74 is probably needed.
Sirherobrine23 commented 2025-11-09 20:33:38 +00:00
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I'm supposed to receive my router tomorrow, but I don't think they'll deliver it tomorrow.

Captura de tela 2025_11_09 17-24-42.png
I'm supposed to receive my router tomorrow, but I don't think they'll deliver it tomorrow. <img width="613" alt="Captura de tela 2025_11_09 17-24-42.png" src="attachments/12a59183-178b-463a-9a2c-ef1a4906ac39">
Captura de tela 2025_11_09 17-24-42.png
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merbanan commented 2025-11-09 20:46:48 +00:00
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Ok, much better. Ping seems stable now.

Ok, much better. Ping seems stable now.
merbanan commented 2025-11-09 20:50:43 +00:00
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Ok, I'm gonna do some other stuff for the time being. Validate my changes when you get your device.

Ok, I'm gonna do some other stuff for the time being. Validate my changes when you get your device.
Sirherobrine23 commented 2025-11-09 20:51:50 +00:00
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okay

okay
merbanan commented 2025-11-09 20:54:07 +00:00
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Ping flood from my computer.

Ping flood from my computer.
Screenshot from 2025-11-09 21-53-40.png
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Screenshot from 2025-11-09 21-53-40.png
👍 1
Sirherobrine23 commented 2025-11-09 21:05:01 +00:00
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Ok, 74 -> 0x74 is probably needed.

GDMP_DATA_SEL to change yep?

kernel/drivers/net/ethernet/airoha/airoha_eth.c Lines 504 to 510 in 7147d32347
if (device_is_compatible(eth->dev, "airoha,en7523-eth")) {
/* map GDMP sram to fe */
#define GDMP_DATA_SEL 74
airoha_wr(eth->gdmp_regs, GDMP_DATA_SEL, 3);
/* set PSE buffer to 0x500 = 0x400(pse itself) + 0x100(GDMP buffer) */
airoha_fe_wr(eth, PSE_FQ_CFG, 0x500);
}

> Ok, 74 -> 0x74 is probably needed. `GDMP_DATA_SEL` to change yep? https://sirherobrine23.com.br/tplink_xx230v/kernel/src/commit/7147d32347e468fbb000a78314a0371212bafba2/drivers/net/ethernet/airoha/airoha_eth.c#L504-L510
merbanan commented 2025-11-09 21:05:50 +00:00
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Yes.

Yes.
👍 1
merbanan commented 2025-11-09 21:59:26 +00:00
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This:

https://econet-linux.pkt.wiki/hardware/EN751221/frame-engine

and the following page 125

https://drive.google.com/file/d/1iZMXhaKoSO1bupRaXUShmNzj9Hj6n9Th/view

describes how things are connected and work.

On the EN7523 it has the WED connected via the GDM3 though and the port indexing has other meanings. But basically there is a PSE with different blocks connected to the PSE ports. And the QDMA is passing packets (descriptors) around.

This: https://econet-linux.pkt.wiki/hardware/EN751221/frame-engine and the following page 125 https://drive.google.com/file/d/1iZMXhaKoSO1bupRaXUShmNzj9Hj6n9Th/view describes how things are connected and work. On the EN7523 it has the WED connected via the GDM3 though and the port indexing has other meanings. But basically there is a PSE with different blocks connected to the PSE ports. And the QDMA is passing packets (descriptors) around.
Sirherobrine23 commented 2025-11-09 22:43:13 +00:00
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so it will be something like this

graph TD
    CPU <--> QDMA1
    CPU --> QDMA2

    subgraph Frame Engine EN7523
        PPE1
        QDMA1
        QDMA2
        NPU
        GDM1
        GDM2
        GDM3
    end

    GDM1 --> MT7530_Switch[MT7530 Switch]
    GDM2 --> WAN_xPON[WAN / xPON]
    GDM3 --> WED["WED/WIFI/HSGMII(USB)/HSGMII(PCIe)"]

    classDef default fill:#D3D3D3,stroke:#333,stroke-width:2px,color:#000;
    classDef highlight fill:#FFE4E1,stroke:#8B0000,stroke-width:2px,color:#000;
    
    class CPU,MT7530_Switch,WAN_xPON,WED highlight
    class Frame_Engine,PPE,QDMA1,GDM1,QDMA2,GDM2 default

graph TD
    subgraph System Bus
        CPU <--> |INT, CFG_REG| PPE
        DRAM <--> QDMA
        TOPS <--> TDMA
        WiFi <--> WED
        CPU <--> ADMA
        DRAM <--> WDMA
        TOPS <--> EIP197
    end

    subgraph "PSE (L3 routing)"
        PPE -- Port #0 <--> PSE
        QDMA -- Port #8,9,13 <--> PSE

        PSE -- p6 <--> L2_Switch_4_port_GPHY
    end

    GMAC_XGMAC2 <--> |2.5G PHY| 2.5G_PHY
    GMAC_XGMAC2 <--> |HSGMII, USXGMII| HSGMII_USXGMII

    GMAC_XGMAC3 <--> |HSGMII, USXGMII| HSGMII_USXGMII

    L2_Switch_4_port_GPHY <--> |p0| RJ45_1
    L2_Switch_4_port_GPHY <--> |p1| RJ45_2
    L2_Switch_4_port_GPHY <--> |p2| RJ45_3
    L2_Switch_4_port_GPHY <--> |p3| RJ45_4

    subgraph Notes
        pse_port_7_drop[PSE port #7 is for packet drop]
        pse_port_6_qdma[PSE port #6 is QDMA HW path]
        pse_port_11_reserved[PSE port #11 is reserved port]
    end

    classDef default fill:#D3D3D3,stroke:#3366cc,stroke-width:2px,color:#000;
    classDef highlight fill:#ADD8E6,stroke:#3366cc,stroke-width:2px,color:#000;
    class CPU,DRAM,TOPS,WiFi,System_Bus,PPE,ADMA,QDMA,WDMA,TDMA,EIP197,WED,PSE,GMAC_XGMAC2,GMAC_XGMAC3,L2_Switch_4_port_GPHY,2.5G_PHY,HSGMII_USXGMII,RJ45_1,RJ45_2,RJ45_3,RJ45_4,note,pse_port_7_drop,pse_port_6_qdma,pse_port_11_reserved default
    class PPE,ADMA,QDMA,WDMA,TDMA,EIP197,WED,GMAC_XGMAC2,GMAC_XGMAC3,L2_Switch_4_port_GPHY highlight
so it will be something like this ```mermaid graph TD CPU <--> QDMA1 CPU --> QDMA2 subgraph Frame Engine EN7523 PPE1 QDMA1 QDMA2 NPU GDM1 GDM2 GDM3 end GDM1 --> MT7530_Switch[MT7530 Switch] GDM2 --> WAN_xPON[WAN / xPON] GDM3 --> WED["WED/WIFI/HSGMII(USB)/HSGMII(PCIe)"] classDef default fill:#D3D3D3,stroke:#333,stroke-width:2px,color:#000; classDef highlight fill:#FFE4E1,stroke:#8B0000,stroke-width:2px,color:#000; class CPU,MT7530_Switch,WAN_xPON,WED highlight class Frame_Engine,PPE,QDMA1,GDM1,QDMA2,GDM2 default ``` ```mermaid graph TD subgraph System Bus CPU <--> |INT, CFG_REG| PPE DRAM <--> QDMA TOPS <--> TDMA WiFi <--> WED CPU <--> ADMA DRAM <--> WDMA TOPS <--> EIP197 end subgraph "PSE (L3 routing)" PPE -- Port #0 <--> PSE QDMA -- Port #8,9,13 <--> PSE PSE -- p6 <--> L2_Switch_4_port_GPHY end GMAC_XGMAC2 <--> |2.5G PHY| 2.5G_PHY GMAC_XGMAC2 <--> |HSGMII, USXGMII| HSGMII_USXGMII GMAC_XGMAC3 <--> |HSGMII, USXGMII| HSGMII_USXGMII L2_Switch_4_port_GPHY <--> |p0| RJ45_1 L2_Switch_4_port_GPHY <--> |p1| RJ45_2 L2_Switch_4_port_GPHY <--> |p2| RJ45_3 L2_Switch_4_port_GPHY <--> |p3| RJ45_4 subgraph Notes pse_port_7_drop[PSE port #7 is for packet drop] pse_port_6_qdma[PSE port #6 is QDMA HW path] pse_port_11_reserved[PSE port #11 is reserved port] end classDef default fill:#D3D3D3,stroke:#3366cc,stroke-width:2px,color:#000; classDef highlight fill:#ADD8E6,stroke:#3366cc,stroke-width:2px,color:#000; class CPU,DRAM,TOPS,WiFi,System_Bus,PPE,ADMA,QDMA,WDMA,TDMA,EIP197,WED,PSE,GMAC_XGMAC2,GMAC_XGMAC3,L2_Switch_4_port_GPHY,2.5G_PHY,HSGMII_USXGMII,RJ45_1,RJ45_2,RJ45_3,RJ45_4,note,pse_port_7_drop,pse_port_6_qdma,pse_port_11_reserved default class PPE,ADMA,QDMA,WDMA,TDMA,EIP197,WED,GMAC_XGMAC2,GMAC_XGMAC3,L2_Switch_4_port_GPHY highlight ```
merbanan commented 2025-11-09 22:58:52 +00:00
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This is the list of ports on the PSE and the component first connected to the port. Other things can be connected after it.

https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/net/ethernet/airoha/airoha_eth.h?h=v6.18-rc4#n114

This is the list of ports on the PSE and the component first connected to the port. Other things can be connected after it. https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/net/ethernet/airoha/airoha_eth.h?h=v6.18-rc4#n114
merbanan commented 2025-11-09 23:17:41 +00:00
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A somewhat interesting gathering of information.

https://github.com/RuijieNetworksCommunity/openwrt-en75xx/blob/en7562-24.10/en7562ct.md

A somewhat interesting gathering of information. https://github.com/RuijieNetworksCommunity/openwrt-en75xx/blob/en7562-24.10/en7562ct.md
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#3 WDMA + WED
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Reference: tplink_xx230v/kernel#2
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