Runyang Chen eb949d9974 feat(mediatek): support write-access for DSU PMU in EL1 ...

Access to the PMU scheme management and thread scheme system registers
from S-EL1/NS-EL1 is controlled by ACTLR_EL3 and ACTLR_EL2. If the
correstonding enables are not set, EL1 write may trap to EL3. To allow
kernel write these registers, it is necessary to enable
write-accessibility.

Change-Id: Ic957193da2542f714341274efba8d2e1903a4f04
Signed-off-by: Runyang Chen <runyang.chen@mediatek.com>

2026-04-21 10:49:31 +00:00

..

armv8_2

feat(mediatek): support write-access for DSU PMU in EL1

2026-04-21 10:49:31 +00:00

armv9

feat(mt8196): initialize platform for MediaTek MT8196

2024-12-02 09:20:48 +08:00

rules.mk

feat(mt8188): add armv8.2 support

2022-09-22 19:26:15 +08:00