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Access to the PMU scheme management and thread scheme system registers from S-EL1/NS-EL1 is controlled by ACTLR_EL3 and ACTLR_EL2. If the correstonding enables are not set, EL1 write may trap to EL3. To allow kernel write these registers, it is necessary to enable write-accessibility. Change-Id: Ic957193da2542f714341274efba8d2e1903a4f04 Signed-off-by: Runyang Chen <runyang.chen@mediatek.com>