forked from dlink-dir_819/openwrt
03a777c293
Refresh uboot-lantiq patches. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> SVN-Revision: 40546
478 lines
11 KiB
Diff
478 lines
11 KiB
Diff
From 1da5479d59b39d7931a2b0efabdfa314f6788b6d Mon Sep 17 00:00:00 2001
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From: Luka Perkov <luka@openwrt.org>
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Date: Sat, 2 Mar 2013 23:34:00 +0100
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Subject: tools: add some helper tools for Lantiq SoCs
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Signed-off-by: Luka Perkov Luka Perkov <luka@openwrt.org>
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Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
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--- /dev/null
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+++ b/tools/gct.pl
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@@ -0,0 +1,155 @@
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+#!/usr/bin/perl
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+
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+#use strict;
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+#use Cwd;
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+#use Env;
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+
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+my $aline;
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+my $lineid;
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+my $length;
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+my $address;
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+my @bytes;
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+my $addstr;
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+my $chsum=0;
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+my $count=0;
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+my $firstime=1;
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+my $i;
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+my $currentaddr;
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+my $tmp;
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+my $holder="";
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+my $loadaddr;
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+
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+if(@ARGV < 2){
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+ die("\n Syntax: perl gct.pl uart_ddr_settings.conf u-boot.srec u-boot.asc\n");
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+}
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+
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+open(IN_UART_DDR_SETTINGS, "<$ARGV[0]") || die("failed to open uart_ddr_settings.conf\n");
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+open(IN_UART_SREC, "<$ARGV[1]") || die("failed to open u-boot.srec\n");
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+open(OUT_UBOOT_ASC, ">$ARGV[2]") || die("failed to open u-boot.asc\n");
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+
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+$i=0;
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+while ($line = <IN_UART_DDR_SETTINGS>){
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+ if($line=~/\w/){
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+ if($line!~/[;#\*]/){
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+ if($i eq 0){
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+ printf OUT_UBOOT_ASC ("33333333");
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+ }
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+ chomp($line);
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+ $line=~s/\t//;
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+ @array=split(/ +/,$line);
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+ $j=0;
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+ while(@array[$j]!~/\w/){
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+ $j=$j+1;
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+ }
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+ $addr=@array[$j];
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+ $regval=@array[$j+1];
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+ $addr=~s/0x//;
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+ $regval=~s/0x//;
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+ printf OUT_UBOOT_ASC ("%08x%08x",hex($addr),hex($regval));
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+ $i=$i+1;
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+ if($i eq 8){
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+ $i=0;
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+ printf OUT_UBOOT_ASC ("\n");
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+ }
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+ }
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+ }
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+}
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+
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+while($i lt 8 && $i gt 0){
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+ printf OUT_UBOOT_ASC "00"x8;
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+ $i=$i+1;
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+}
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+
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+if($i eq 8){
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+ printf OUT_UBOOT_ASC ("\n");
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+}
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+
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+while($aline=<IN_UART_SREC>){
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+ $aline=uc($aline);
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+ chomp($aline);
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+ next if(($aline=~/^S0/) || ($aline=~/^S7/));
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+ ($lineid, $length, $address, @bytes) = unpack"A2A2A8"."A2"x300, $aline;
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+ $length = hex($length);
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+ $address = hex($address);
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+ $length -=5;
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+ $i=0;
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+
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+ while($length>0){
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+ if($firstime==1){
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+ $addstr = sprintf("%x", $address);
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+ $addstr = "0"x(8-length($addstr)).$addstr;
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+ print OUT_UBOOT_ASC $addstr;
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+ addchsum($addstr);
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+ $firstime=0;
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+ $currentaddr=$address;
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+ $loadaddr = $addstr;
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+ }
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+ else{
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+ if($count==64){
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+ $addstr = sprintf("%x", $currentaddr);
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+ $addstr = "0"x(8-length($addstr)).$addstr;
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+ print OUT_UBOOT_ASC $addstr;
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+ addchsum($addstr);
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+ $count=0;
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+ }
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+#printf("*** %x != %x\n", $address, $currentaddr) if $address != $currentaddr;
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+ }
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+ if($currentaddr < $address) {
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+ print OUT_UBOOT_ASC "00";
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+ addchsum("00");
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+ $count++;
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+ $currentaddr++;
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+ }
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+ else {
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+ while($count<64){
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+ $bytes[$i]=~tr/ABCDEF/abcdef/;
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+ print OUT_UBOOT_ASC "$bytes[$i]";
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+ addchsum($bytes[$i]);
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+ $i++;
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+ $count++;
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+ $currentaddr++;
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+ $length--;
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+ last if($length==0);
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+ }
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+ }
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+ if($count==64){
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+ print OUT_UBOOT_ASC "\n";
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+ }
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+ }
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+}
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+if($count != 64){
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+ $tmp = "00";
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+ for($i=0;$i<(64-$count);$i++){
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+ print OUT_UBOOT_ASC "00";
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+ addchsum($tmp);
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+ }
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+ print OUT_UBOOT_ASC "\n";
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+}
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+
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+
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+print OUT_UBOOT_ASC "11"x4;
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+use integer;
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+$chsum=$chsum & 0xffffffff;
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+$chsum = sprintf("%X", $chsum);
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+$chsum = "0"x(8-length($chsum)).$chsum;
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+$chsum =~tr/ABCDEF/abcdef/;
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+print OUT_UBOOT_ASC $chsum;
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+print OUT_UBOOT_ASC "00"x60;
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+print OUT_UBOOT_ASC "\n";
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+
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+print OUT_UBOOT_ASC "99"x4;
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+print OUT_UBOOT_ASC $loadaddr;
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+print OUT_UBOOT_ASC "00"x60;
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+print OUT_UBOOT_ASC "\n";
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+
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+close OUT_UBOOT_ASC;
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+
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+sub addchsum{
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+ my $cc=$_[0];
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+ $holder=$holder.$cc;
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+ if(length($holder)==8){
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+ $holder = hex($holder);
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+ $chsum+=$holder;
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+ $holder="";
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+ }
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+}
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--- /dev/null
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+++ b/tools/lantiq_bdi_conf.awk
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@@ -0,0 +1,116 @@
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+#!/usr/bin/awk -f
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+#
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+# Copyright (C) 2013 Luka Perkov <luka@openwrt.org>
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+# Copyright (C) 2013 Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
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+#
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+# Usage:
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+# awk -f lantiq_bdi_conf.awk -v soc=ar9 board=<name> PATH_TO_BOARD/ddr_settings.h
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+#
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+# Additional information:
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+# http://www.abatron.ch/fileadmin/user_upload/products/pdf/ManGDBR4K-3000.pdf
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+#
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+# SPDX-License-Identifier: GPL-2.0+
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+#
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+
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+function print_header()
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+{
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+ print "; "
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+ print "; Copyright (C) 2013 Luka Perkov <luka@openwrt.org> "
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+ print "; Copyright (C) 2013 Daniel Schwierzeck <daniel.schwierzeck@gmail.com> "
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+ print "; "
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+ print "; This file has been generated with lantiq_bdi_conf.awk script. "
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+ print "; "
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+ print "; SPDX-License-Identifier: GPL-2.0+ "
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+ print "; "
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+ print ""
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+}
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+
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+function init_ar9_prologue()
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+{
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+ print "WM32 0xBF103010 0x80 ; CGU for CPU 333Mhz, DDR 167Mhz"
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+ print "WM32 0xBF103014 0x01 ; CGU update"
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+ print "WM32 0xBF800010 0x0 ; Clear error access log register"
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+ print "WM32 0xBF800020 0x0 ; Clear error access log register"
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+ print "WM32 0xBF800060 0xD ; Enable FPI, DDR and SRAM module in memory controller"
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+ print "WM32 0xBF801030 0x0 ; Clear start bit of DDR memory controller"
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+}
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+
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+function init_ar9_epilogue()
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+{
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+ print "WM32 0xBE105360 0x4001D7FF ; EBU setup"
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+}
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+
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+function init_ddr1_epilogue()
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+{
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+ print "WM32 0xBF801030 0x100 ; Set start bit of DDR memory controller"
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+}
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+
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+function ar9_target()
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+{
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+ print "CPUTYPE M34K"
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+ print "ENDIAN BIG"
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+ print "JTAGCLOCK 1"
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+ print "BDIMODE AGENT ; [ LOADONLY, AGENT ]"
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+ print "RESET JTAG ; [ NONE, JTAG, HARD ]"
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+ print "POWERUP 100"
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+ print "WAKEUP 100"
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+ print "BREAKMODE HARD ; [ SOFT, HARD ]"
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+ print "STEPMODE SWBP ; [ JTAG, HWBP, SWBP ]"
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+ print "VECTOR CATCH"
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+ print "SCANSUCC 1 5"
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+}
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+
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+function flash_p2601hnfx()
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+{
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+ print "CHIPTYPE MIRRORX16"
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+ print "CHIPSIZE 0x1000000"
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+ print "BUSWIDTH 16"
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+}
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+
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+BEGIN {
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+ switch (soc) {
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+ case "ar9":
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+ reg_base = 0xbf801000
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+ print_header()
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+ print "[INIT]"
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+ init_ar9_prologue()
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+ break
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+ default:
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+ print "Invalid or no value for SoC specified!"
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+ exit 1
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+ }
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+}
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+
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+/^#define/ {
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+ /* DC03 contains MC enable bit and must not be set here */
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+ if (tolower($2) != "mc_dc03_value")
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+ printf("WM32 0x%x %s\n", reg_base, tolower($3))
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+
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+ reg_base += 0x10
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+}
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+
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+END {
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+ switch (soc) {
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+ case "ar9":
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+ init_ddr1_epilogue()
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+ init_ar9_epilogue()
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+ print ""
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+ print "[TARGET]"
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+ ar9_target()
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+ print ""
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+ print "[HOST]"
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+ print "PROMPT \"ar9> \""
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+ print ""
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+ break
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+ default:
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+ }
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+
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+ switch (board) {
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+ case "p2601hnfx":
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+ print "[FLASH]"
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+ flash_p2601hnfx()
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+ print ""
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+ break
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+ default:
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+ }
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+}
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--- /dev/null
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+++ b/tools/lantiq_ram_extract_magic.awk
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@@ -0,0 +1,69 @@
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+#
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+# Copyright (C) 2011-2013 Luka Perkov <luka@openwrt.org>
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+#
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+# Usage:
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+# mips-openwrt-linux-objdump -EB -b binary -m mips:isa32r2 -D YOUR_IMAGE_DUMP | awk -f lantiq_ram_extract_magic.awk
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+#
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+# SPDX-License-Identifier: GPL-2.0+
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+#
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+
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+BEGIN {
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+ print "/* "
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+ print " * Copyright (C) 2011-2013 Luka Perkov <luka@openwrt.org> "
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+ print " * "
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+ print " * This file has been generated with lantiq_ram_extract_magic.awk script. "
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+ print " * "
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+ print " * SPDX-License-Identifier: GPL-2.0+ "
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+ print " */ "
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+ print ""
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+
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+ mc_dc_value=0
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+ mc_dc_number=0
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+ right_section=0
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+ mc_dc_value_print=0
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+ mc_dc_number_print=0
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+}
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+
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+/t2,[0-9]+$/ {
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+ if (right_section) {
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+ split($4, tmp, ",")
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+ mc_dc_value=sprintf("%X", tmp[2])
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+ mc_dc_value_print=1
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+ }
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+}
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+
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+/t2,0x[0-9a-f]+$/ {
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+ if (right_section) {
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+ split($4, tmp, ",0x")
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+ mc_dc_value=sprintf("%s", tmp[2])
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+ mc_dc_value=toupper(mc_dc_value)
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+ mc_dc_value_print=1
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+ }
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+}
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+
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+/t2,[0-9]+\(t1\)$/ {
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+ if (right_section) {
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+ split($4, tmp, ",")
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+ split(tmp[2], tmp, "(")
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+ mc_dc_number=tmp[1]/16
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+ mc_dc_number_print=1
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+ }
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+}
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+
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+{
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+ if (right_section && mc_dc_number_print && mc_dc_value_print) {
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+ if (mc_dc_number < 10)
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+ print "#define MC_DC0" mc_dc_number "_VALUE\t0x" mc_dc_value
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+ else
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+ print "#define MC_DC" mc_dc_number "_VALUE\t0x" mc_dc_value
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+ mc_dc_value_print=0
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+ mc_dc_number_print=0
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+ }
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+
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+ if ($4 == "t1,t1,0x1000")
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+ right_section=1
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+
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+
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+ if ($4 == "t2,736(t1)")
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+ right_section=0
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+}
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--- /dev/null
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+++ b/tools/lantiq_ram_init_uart.awk
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@@ -0,0 +1,117 @@
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+#!/usr/bin/awk -f
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+#
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+# Copyright (C) 2011-2012 Luka Perkov <luka@openwrt.org>
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+# Copyright (C) 2012 Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
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+#
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+# Usage:
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+# awk -f lantiq_ram_init_uart.awk -v soc=<danube|ar9|vr9> PATH_TO_BOARD/ddr_settings.h
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+#
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+# SPDX-License-Identifier: GPL-2.0+
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+#
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+
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+function print_header()
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+{
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+ print "; "
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+ print "; Copyright (C) 2011-2013 Luka Perkov <luka@openwrt.org> "
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+ print "; Copyright (C) 2012-2013 Daniel Schwierzeck <daniel.schwierzeck@gmail.com> "
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+ print "; "
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+ print "; This file has been generated with lantiq_ram_init_uart.awk script. "
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+ print "; "
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+ print "; SPDX-License-Identifier: GPL-2.0+ "
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+ print ""
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+}
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+
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+function mc_danube_prologue()
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+{
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+ /* Clear access error log registers */
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+ print "0xbf800010", "0x0"
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+ print "0xbf800020", "0x0"
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+
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+ /* Enable DDR and SRAM module in memory controller */
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+ print "0xbf800060", "0x5"
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+
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+ /* Clear start bit of DDR memory controller */
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+ print "0xbf801030", "0x0"
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+}
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+
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+function mc_ar9_prologue()
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+{
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+ /* Clear access error log registers */
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+ print "0xbf800010", "0x0"
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+ print "0xbf800020", "0x0"
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+
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+ /* Enable FPI, DDR and SRAM module in memory controller */
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+ print "0xbf800060", "0xD"
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+
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+ /* Clear start bit of DDR memory controller */
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+ print "0xbf801030", "0x0"
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+}
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+
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+function mc_ddr1_epilogue()
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+{
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+ /* Set start bit of DDR memory controller */
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+ print "0xbf801030", "0x100"
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+}
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+
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+function mc_ddr2_prologue()
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+{
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+ /* Put memory controller in inactive mode */
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+ print "0xbf401070", "0x0"
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+}
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+
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+function mc_ddr2_epilogue(mc_ccr07_value)
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+{
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+ /* Put memory controller in active mode */
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+ mc_ccr07_value = or(mc_ccr07_value, 0x100)
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+ printf("0xbf401070 0x%x\n", mc_ccr07_value)
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+}
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+
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+BEGIN {
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+ switch (soc) {
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+ case "danube":
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+ reg_base = 0xbf801000
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+ print_header()
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+ mc_danube_prologue()
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+ break
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+ case "ar9":
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+ reg_base = 0xbf801000
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+ print_header()
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+ mc_ar9_prologue()
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+ break
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+ case "vr9":
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+ reg_base = 0xbf401000
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+ print_header()
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+ mc_ddr2_prologue()
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+ break
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+ default:
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+ print "Invalid or no value for soc specified!"
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+ exit 1
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+ }
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+
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+ mc_ccr07_value = 0
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+}
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+
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+/^#define/ {
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+ /* CCR07 contains MC enable bit and must not be set here */
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+ if (tolower($2) == "mc_ccr07_value")
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+ mc_ccr07_value = strtonum($3)
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+ if (tolower($2) == "mc_dc03_value")
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+ /* CCR07 contains MC enable bit and must not be set here */
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+ else
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+ printf("0x%x %s\n", reg_base, tolower($3))
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+
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+ reg_base += 0x10
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+}
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+
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+END {
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+ switch (soc) {
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+ case "danube":
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+ case "ar9":
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+ mc_ddr1_epilogue()
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+ break
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+ case "vr9":
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+ mc_ddr2_epilogue(mc_ccr07_value)
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+ break
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+ default:
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+ }
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+}
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