forked from dlink-dir_819/openwrt
d41d9befb9
Add u-boot bootloader based on 2023.01 to support D1-based boards, currently: - Dongshan Nezha STU - LicheePi RV Dock - MangoPi MQ-Pro - Nezha D1 Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
52 lines
1.5 KiB
Diff
52 lines
1.5 KiB
Diff
From ca1e6f4491981432c3e88441131c8e25067da95e Mon Sep 17 00:00:00 2001
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From: Samuel Holland <samuel@sholland.org>
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Date: Sat, 9 Oct 2021 22:00:22 -0500
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Subject: [PATCH 26/90] sunxi: psci: Avoid hanging when CPU 0 is hot-unplugged
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Do not try to send an SGI from CPU 0 to itself. Since FIQs are masked
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when entering monitor mode, this will hang. Plus, CPU 0 cannot fully
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power itself off anyway. Instead, have it turn FIQs back on and continue
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servicing SGIs from other cores.
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Signed-off-by: Samuel Holland <samuel@sholland.org>
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---
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arch/arm/cpu/armv7/sunxi/psci.c | 20 +++++++++++++++++---
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1 file changed, 17 insertions(+), 3 deletions(-)
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--- a/arch/arm/cpu/armv7/sunxi/psci.c
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+++ b/arch/arm/cpu/armv7/sunxi/psci.c
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@@ -38,6 +38,15 @@
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#define SUN8I_R40_PWR_CLAMP(cpu) (0x120 + (cpu) * 0x4)
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#define SUN8I_R40_SRAMC_SOFT_ENTRY_REG0 (0xbc)
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+static inline u32 __secure cp15_read_mpidr(void)
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+{
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+ u32 val;
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+
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+ asm volatile ("mrc p15, 0, %0, c0, c0, 5" : "=r" (val));
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+
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+ return val;
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+}
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+
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static void __secure cp15_write_cntp_tval(u32 tval)
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{
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asm volatile ("mcr p15, 0, %0, c14, c2, 0" : : "r" (tval));
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@@ -281,9 +290,14 @@ s32 __secure psci_cpu_off(void)
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{
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psci_cpu_off_common();
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- /* Ask CPU0 via SGI15 to pull the rug... */
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- writel(BIT(16) | 15, GICD_BASE + GICD_SGIR);
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- dsb();
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+ if (cp15_read_mpidr() & 3) {
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+ /* Ask CPU0 via SGI15 to pull the rug... */
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+ writel(BIT(16) | 15, GICD_BASE + GICD_SGIR);
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+ dsb();
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+ } else {
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+ /* Unmask FIQs to service SGI15. */
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+ asm volatile ("cpsie f");
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+ }
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/* Wait to be turned off */
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while (1)
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