forked from dlink-dir_819/openwrt
d41d9befb9
Add u-boot bootloader based on 2023.01 to support D1-based boards, currently: - Dongshan Nezha STU - LicheePi RV Dock - MangoPi MQ-Pro - Nezha D1 Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
161 lines
4.6 KiB
Diff
161 lines
4.6 KiB
Diff
From 5a909f4d4d10f3a7a59b3b75eee502937e166891 Mon Sep 17 00:00:00 2001
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From: Samuel Holland <samuel@sholland.org>
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Date: Mon, 2 May 2022 22:00:05 -0500
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Subject: [PATCH 13/90] clk: sunxi: Add a driver for the legacy A31/A23/A33
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PRCM
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Signed-off-by: Samuel Holland <samuel@sholland.org>
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---
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drivers/clk/sunxi/Kconfig | 13 ++++-
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drivers/clk/sunxi/Makefile | 1 +
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drivers/clk/sunxi/clk_a31_apb0.c | 97 ++++++++++++++++++++++++++++++++
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include/clk/sunxi.h | 1 +
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4 files changed, 110 insertions(+), 2 deletions(-)
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create mode 100644 drivers/clk/sunxi/clk_a31_apb0.c
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--- a/drivers/clk/sunxi/Kconfig
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+++ b/drivers/clk/sunxi/Kconfig
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@@ -38,12 +38,21 @@ config CLK_SUN6I_A31
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This enables common clock driver support for platforms based
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on Allwinner A31/A31s SoC.
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+config CLK_SUN6I_A31_APB0
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+ bool "Clock driver for Allwinner A31 generation PRCM (legacy)"
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+ default MACH_SUN6I || MACH_SUN8I_A23 || MACH_SUN8I_A33
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+ help
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+ This enables common clock driver support for the PRCM
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+ in Allwinner A31/A31s/A23/A33 SoCs using the legacy PRCM
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+ MFD binding.
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+
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config CLK_SUN6I_A31_R
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- bool "Clock driver for Allwinner A31 generation PRCM"
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+ bool "Clock driver for Allwinner A31 generation PRCM (CCU)"
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default SUNXI_GEN_SUN6I
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help
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This enables common clock driver support for the PRCM
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- in Allwinner A31/A31s/A23/A33/A83T/H3/A64/H5 SoCs.
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+ in Allwinner A31/A31s/A23/A33/A83T/H3/A64/H5 SoCs using
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+ the new CCU binding.
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config CLK_SUN8I_A23
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bool "Clock driver for Allwinner A23/A33"
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--- a/drivers/clk/sunxi/Makefile
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+++ b/drivers/clk/sunxi/Makefile
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@@ -12,6 +12,7 @@ obj-$(CONFIG_CLK_SUNIV_F1C100S) += clk_f
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obj-$(CONFIG_CLK_SUN4I_A10) += clk_a10.o
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obj-$(CONFIG_CLK_SUN5I_A10S) += clk_a10s.o
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obj-$(CONFIG_CLK_SUN6I_A31) += clk_a31.o
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+obj-$(CONFIG_CLK_SUN6I_A31_APB0) += clk_a31_apb0.o
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obj-$(CONFIG_CLK_SUN6I_A31_R) += clk_a31_r.o
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obj-$(CONFIG_CLK_SUN8I_A23) += clk_a23.o
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obj-$(CONFIG_CLK_SUN8I_A83T) += clk_a83t.o
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--- /dev/null
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+++ b/drivers/clk/sunxi/clk_a31_apb0.c
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@@ -0,0 +1,97 @@
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+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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+/*
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+ * Copyright (C) Samuel Holland <samuel@sholland.org>
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+ */
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+
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+#include <clk-uclass.h>
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+#include <dm.h>
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+#include <clk/sunxi.h>
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+#include <linux/bitops.h>
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+
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+static struct ccu_clk_gate sun6i_apb0_gates[] = {
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+ [0] = GATE(0x028, BIT(0)),
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+ [1] = GATE(0x028, BIT(1)),
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+ [2] = GATE(0x028, BIT(2)),
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+ [3] = GATE(0x028, BIT(3)),
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+ [4] = GATE(0x028, BIT(4)),
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+ [5] = GATE(0x028, BIT(5)),
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+ [6] = GATE(0x028, BIT(6)),
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+ [7] = GATE(0x028, BIT(7)),
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+};
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+
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+static struct ccu_reset sun6i_apb0_resets[] = {
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+ [0] = RESET(0x0b0, BIT(0)),
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+ [1] = RESET(0x0b0, BIT(1)),
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+ [2] = RESET(0x0b0, BIT(2)),
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+ [3] = RESET(0x0b0, BIT(3)),
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+ [4] = RESET(0x0b0, BIT(4)),
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+ [5] = RESET(0x0b0, BIT(5)),
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+ [6] = RESET(0x0b0, BIT(6)),
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+ [7] = RESET(0x0b0, BIT(7)),
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+};
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+
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+const struct ccu_desc sun6i_apb0_clk_desc = {
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+ .gates = sun6i_apb0_gates,
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+ .resets = sun6i_apb0_resets,
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+ .num_gates = ARRAY_SIZE(sun6i_apb0_gates),
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+ .num_resets = ARRAY_SIZE(sun6i_apb0_resets),
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+};
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+
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+static int sun6i_apb0_of_to_plat(struct udevice *dev)
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+{
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+ struct ccu_plat *plat = dev_get_plat(dev);
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+
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+ plat->base = dev_read_addr_ptr(dev->parent);
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+ if (!plat->base)
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+ return -ENOMEM;
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+
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+ plat->desc = (const struct ccu_desc *)dev_get_driver_data(dev);
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+ if (!plat->desc)
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+ return -EINVAL;
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+
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+ return 0;
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+}
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+
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+static const struct udevice_id sun6i_apb0_clk_ids[] = {
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+ { .compatible = "allwinner,sun6i-a31-apb0-gates-clk",
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+ .data = (ulong)&sun6i_apb0_clk_desc },
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+ { .compatible = "allwinner,sun8i-a23-apb0-gates-clk",
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+ .data = (ulong)&sun6i_apb0_clk_desc },
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+ { }
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+};
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+
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+U_BOOT_DRIVER(sun6i_apb0_clk) = {
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+ .name = "sun6i_apb0_clk",
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+ .id = UCLASS_CLK,
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+ .of_match = sun6i_apb0_clk_ids,
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+ .of_to_plat = sun6i_apb0_of_to_plat,
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+ .plat_auto = sizeof(struct ccu_plat),
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+ .ops = &sunxi_clk_ops,
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+};
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+
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+static const struct udevice_id sun6i_apb0_reset_ids[] = {
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+ { .compatible = "allwinner,sun6i-a31-clock-reset",
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+ .data = (ulong)&sun6i_apb0_clk_desc },
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+ { }
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+};
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+
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+U_BOOT_DRIVER(sun6i_apb0_reset) = {
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+ .name = "sun6i_apb0_reset",
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+ .id = UCLASS_RESET,
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+ .of_match = sun6i_apb0_reset_ids,
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+ .of_to_plat = sun6i_apb0_of_to_plat,
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+ .plat_auto = sizeof(struct ccu_plat),
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+ .ops = &sunxi_reset_ops,
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+};
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+
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+static const struct udevice_id sun6i_prcm_mfd_ids[] = {
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+ { .compatible = "allwinner,sun6i-a31-prcm" },
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+ { .compatible = "allwinner,sun8i-a23-prcm" },
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+ { }
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+};
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+
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+U_BOOT_DRIVER(sun6i_prcm_mfd) = {
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+ .name = "sun6i_prcm_mfd",
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+ .id = UCLASS_SIMPLE_BUS,
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+ .of_match = sun6i_prcm_mfd_ids,
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+};
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--- a/include/clk/sunxi.h
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+++ b/include/clk/sunxi.h
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@@ -86,5 +86,6 @@ struct ccu_plat {
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};
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extern struct clk_ops sunxi_clk_ops;
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+extern struct reset_ops sunxi_reset_ops;
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#endif /* _CLK_SUNXI_H */
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