71 lines
2.1 KiB
Diff
71 lines
2.1 KiB
Diff
From 0568e7f92ecf2bfd2af0a5c59b1249fef002c89f Mon Sep 17 00:00:00 2001
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From: Gabor Juhos <juhosg@openwrt.org>
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Date: Tue, 3 Jul 2012 10:24:43 +0200
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Subject: [PATCH 24/34] MIPS: ath79: add WMAC registration code for the QCA955X SoCs
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Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
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---
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arch/mips/ath79/Kconfig | 2 +-
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arch/mips/ath79/dev-wmac.c | 20 ++++++++++++++++++++
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arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 2 ++
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3 files changed, 23 insertions(+), 1 deletions(-)
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--- a/arch/mips/ath79/Kconfig
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+++ b/arch/mips/ath79/Kconfig
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@@ -108,7 +108,7 @@ config ATH79_DEV_USB
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def_bool n
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config ATH79_DEV_WMAC
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- depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X)
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+ depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X || SOC_QCA955X)
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def_bool n
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endif
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--- a/arch/mips/ath79/dev-wmac.c
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+++ b/arch/mips/ath79/dev-wmac.c
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@@ -116,6 +116,24 @@ static void ar934x_wmac_setup(void)
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ath79_wmac_data.is_clk_25mhz = true;
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}
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+static void qca955x_wmac_setup(void)
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+{
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+ u32 t;
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+
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+ ath79_wmac_device.name = "qca955x_wmac";
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+
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+ ath79_wmac_resources[0].start = QCA955X_WMAC_BASE;
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+ ath79_wmac_resources[0].end = QCA955X_WMAC_BASE + QCA955X_WMAC_SIZE - 1;
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+ ath79_wmac_resources[1].start = ATH79_IP2_IRQ(1);
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+ ath79_wmac_resources[1].start = ATH79_IP2_IRQ(1);
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+
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+ t = ath79_reset_rr(QCA955X_RESET_REG_BOOTSTRAP);
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+ if (t & QCA955X_BOOTSTRAP_REF_CLK_40)
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+ ath79_wmac_data.is_clk_25mhz = false;
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+ else
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+ ath79_wmac_data.is_clk_25mhz = true;
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+}
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+
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void __init ath79_register_wmac(u8 *cal_data)
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{
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if (soc_is_ar913x())
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@@ -124,6 +142,8 @@ void __init ath79_register_wmac(u8 *cal_
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ar933x_wmac_setup();
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else if (soc_is_ar934x())
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ar934x_wmac_setup();
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+ else if (soc_is_qca955x())
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+ qca955x_wmac_setup();
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else
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BUG();
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--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
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+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
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@@ -94,6 +94,8 @@
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#define AR934X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000)
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#define AR934X_SRIF_SIZE 0x1000
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+#define QCA955X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
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+#define QCA955X_WMAC_SIZE 0x20000
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#define QCA955X_EHCI0_BASE 0x1b000000
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#define QCA955X_EHCI1_BASE 0x1b400000
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#define QCA955X_EHCI_SIZE 0x200
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