mirror of
https://git.openwrt.org/openwrt/openwrt.git
synced 2025-10-28 17:15:47 +00:00
ae7fc18cf2
Specification:
- SoC : MediaTek MT7621AT, dual-core 880 MHz MIPS CPU
- RAM : DDR3 512 MB (Micron MT41K256M16TW-107)
- Flash : SPI-NOR 16 MB (MACRONIX MX25L12835FM2I-10G)
- Ethernet : 5 port GbE Switch
- LAN :
3x RJ-45 Port
1x PHD Connector (2x5 pin, pitch 2.0 mm)
- WAN :
1x RJ-45 Port
- LED : 8x LEDs
1x Power (Blue)
2x MiniPCIe (Orange)
1x M.2 B Key (Red)
4x Ethernet activity (White)
- UART : 1x4 pin header on PCB [J1]
- arrangement : 3.3V, TX, RX, GND
- settings : 57600, 8n1
- Button : 2x (Reset, WPS)
- USB : 1x USB 2.0
- Socket :
2x MiniPCIe (PCIe Gen2)
1x M.2 B key (PCIe Gen2 + USB 3.0)
1x MicroSD
1x SIM Card
- Power : 12V DC, 1A
MAC addresses :
LAN: 00:0A:52:xx:xx:xx (Factory, 0xe000)
WAN: 00:0A:52:xx:xx:xx (Factory, 0xe006)
Flash instruction through LuCI:
This device is flashed OpenWRT base firmware with this target.
The LuCI webpage is integrated in default for upgrading.
Flash instruction through u-boot:
1. Prepare the TFTP server on PC.
2. Connect uart to PC, select "2. Upgrade firmware" in u-boot menu.
3. Select "0 - TFTP client (Default)", input client IP, server IP, flashed bin file path
4. Wait about 60 seconds to complete flashing
Signed-off-by: Elwin Huang <s09289728096@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/19944
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
139 lines
2.0 KiB
Plaintext
Executable File
139 lines
2.0 KiB
Plaintext
Executable File
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
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#include "mt7621.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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/ {
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compatible = "asiarf,ap7621-004-v3", "mediatek,mt7621-soc";
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model = "AsiaRF AP7621-004 v3";
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keys {
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compatible = "gpio-keys";
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wps {
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label = "wps";
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gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_WPS_BUTTON>;
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};
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reset {
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label = "reset";
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gpios = <&gpio 18 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_RESTART>;
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};
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};
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};
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&sdhci {
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status = "okay";
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non-removable;
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};
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&spi0 {
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status = "okay";
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flash@0 {
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <40000000>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "u-boot";
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reg = <0x0 0x30000>;
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read-only;
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};
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partition@30000 {
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label = "u-boot-env";
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reg = <0x30000 0x10000>;
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};
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partition@40000 {
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label = "factory";
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reg = <0x40000 0x10000>;
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read-only;
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nvmem-layout {
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compatible = "fixed-layout";
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#address-cells = <1>;
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#size-cells = <1>;
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macaddr_factory_e000: macaddr@e000 {
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reg = <0xe000 0x6>;
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};
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macaddr_factory_e006: macaddr@e006 {
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reg = <0xe006 0x6>;
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};
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};
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};
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partition@50000 {
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label = "firmware";
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reg = <0x50000 0xfb0000>;
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compatible = "denx,uimage";
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};
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};
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};
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};
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&pcie {
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status = "okay";
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};
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ðernet {
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pinctrl-0 = <&mdio_pins>, <&rgmii1_pins>;
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};
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&gmac0 {
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status = "okay";
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nvmem-cell-names = "mac-address";
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nvmem-cells = <&macaddr_factory_e000>;
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};
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&switch0 {
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ports {
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port@0 {
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status = "okay";
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label = "wan";
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nvmem-cell-names = "mac-address";
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nvmem-cells = <&macaddr_factory_e006>;
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};
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port@1 {
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status = "okay";
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label = "lan1";
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};
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port@2 {
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status = "okay";
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label = "lan2";
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};
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port@3 {
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status = "okay";
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label = "lan3";
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};
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port@4 {
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status = "okay";
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label = "lan4";
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};
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};
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};
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&state_default {
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gpio {
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groups = "wdt", "jtag";
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function = "gpio";
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};
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};
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