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c3a94894c9
This is an automatically generated commit. When doing `git bisect`, consider `git bisect --skip`. Signed-off-by: Pawel Dembicki <paweldembicki@gmail.com> Link: https://github.com/openwrt/openwrt/pull/19152 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
35 lines
1002 B
Diff
35 lines
1002 B
Diff
From 38093ebbf25eb60a1aa863f46118a68a0300c56e Mon Sep 17 00:00:00 2001
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From: Kuldeep Singh <kuldeep.singh@nxp.com>
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Date: Fri, 3 Jan 2020 14:49:07 +0530
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Subject: [PATCH] arm64: dts: ls1046a-rdb: Update qspi spi-rx-bus-width to 1
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Update rx width from quad mode to single mode as a workaround.
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[Leo: Local workaround ]
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Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com>
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---
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arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts | 4 ++--
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1 file changed, 2 insertions(+), 2 deletions(-)
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--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
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+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
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@@ -104,7 +104,7 @@
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#address-cells = <1>;
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#size-cells = <1>;
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spi-max-frequency = <50000000>;
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- spi-rx-bus-width = <4>;
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+ spi-rx-bus-width = <1>;
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spi-tx-bus-width = <1>;
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reg = <0>;
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};
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@@ -114,7 +114,7 @@
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#address-cells = <1>;
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#size-cells = <1>;
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spi-max-frequency = <50000000>;
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- spi-rx-bus-width = <4>;
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+ spi-rx-bus-width = <1>;
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spi-tx-bus-width = <1>;
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reg = <1>;
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};
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