mirror of
https://git.code.sf.net/p/openocd/code
synced 2024-11-14 18:37:11 +00:00
09ca11066b
With commit dc7b32ea4a00 ("armv7m_trace: get rid of the old tpiu
code") the target's event "trace-config" has been deprecated.
Create the TPIU device.
Replace the target's event "trace-config" with tpiu's event
"pre-enable" in the STM32 devices that require enabling the trace
clock _before_ programming the TPIU.
Make the script multi-instance-able in case it's used for JTAG
chained devices.
Uniform the code in STM32F4x with the other scripts.
Remove the empty event from STM32WLx.
Change-Id: Ifda219c3c5f37e03072a88168611cf505eb630b7
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6681
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
99 lines
2.5 KiB
INI
99 lines
2.5 KiB
INI
# SPDX-License-Identifier: GPL-2.0-or-later
|
|
|
|
# script for stm32f1x family
|
|
|
|
#
|
|
# stm32 devices support both JTAG and SWD transports.
|
|
#
|
|
source [find target/swj-dp.tcl]
|
|
source [find mem_helper.tcl]
|
|
|
|
if { [info exists CHIPNAME] } {
|
|
set _CHIPNAME $CHIPNAME
|
|
} else {
|
|
set _CHIPNAME stm32f1x
|
|
}
|
|
|
|
set _ENDIAN little
|
|
|
|
# Work-area is a space in RAM used for flash programming
|
|
# By default use 4kB (as found on some STM32F100s)
|
|
if { [info exists WORKAREASIZE] } {
|
|
set _WORKAREASIZE $WORKAREASIZE
|
|
} else {
|
|
set _WORKAREASIZE 0x1000
|
|
}
|
|
|
|
# Allow overriding the Flash bank size
|
|
if { [info exists FLASH_SIZE] } {
|
|
set _FLASH_SIZE $FLASH_SIZE
|
|
} else {
|
|
# autodetect size
|
|
set _FLASH_SIZE 0
|
|
}
|
|
|
|
#jtag scan chain
|
|
if { [info exists CPUTAPID] } {
|
|
set _CPUTAPID $CPUTAPID
|
|
} else {
|
|
if { [using_jtag] } {
|
|
# See STM Document RM0008 Section 26.6.3
|
|
set _CPUTAPID 0x3ba00477
|
|
} {
|
|
# this is the SW-DP tap id not the jtag tap id
|
|
set _CPUTAPID 0x1ba01477
|
|
}
|
|
}
|
|
|
|
swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
|
|
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
|
|
|
|
if {[using_jtag]} {
|
|
jtag newtap $_CHIPNAME bs -irlen 5
|
|
}
|
|
|
|
set _TARGETNAME $_CHIPNAME.cpu
|
|
target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
|
|
|
|
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
|
|
|
|
# flash size will be probed
|
|
set _FLASHNAME $_CHIPNAME.flash
|
|
flash bank $_FLASHNAME stm32f1x 0x08000000 $_FLASH_SIZE 0 0 $_TARGETNAME
|
|
|
|
# JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz
|
|
adapter speed 1000
|
|
|
|
adapter srst delay 100
|
|
if {[using_jtag]} {
|
|
jtag_ntrst_delay 100
|
|
}
|
|
|
|
reset_config srst_nogate
|
|
|
|
if {![using_hla]} {
|
|
# if srst is not fitted use SYSRESETREQ to
|
|
# perform a soft reset
|
|
cortex_m reset_config sysresetreq
|
|
}
|
|
|
|
$_TARGETNAME configure -event examine-end {
|
|
# DBGMCU_CR |= DBG_WWDG_STOP | DBG_IWDG_STOP |
|
|
# DBG_STANDBY | DBG_STOP | DBG_SLEEP
|
|
mmw 0xE0042004 0x00000307 0
|
|
}
|
|
|
|
tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000
|
|
|
|
lappend _telnet_autocomplete_skip _proc_pre_enable_$_CHIPNAME.tpiu
|
|
proc _proc_pre_enable_$_CHIPNAME.tpiu {_targetname} {
|
|
targets $_targetname
|
|
|
|
# Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
|
|
# change this value accordingly to configure trace pins
|
|
# assignment
|
|
mmw 0xE0042004 0x00000020 0
|
|
}
|
|
|
|
$_CHIPNAME.tpiu configure -event pre-enable "_proc_pre_enable_$_CHIPNAME.tpiu $_TARGETNAME"
|