openocd/tcl/target/st/stm32mp21x.cfg

# SPDX-License-Identifier: GPL-2.0-or-later

# STMicroelectronics STM32MP21x
# STM32MP21x devices support both JTAG and SWD transports.

# HLA does not support multi-cores nor custom CSW nor AP other than 0
if { [using_hla] } {
	echo "ERROR: HLA transport cannot work with this target."
	shutdown
}

source [find target/swj-dp.tcl]
source [find mem_helper.tcl]

if { [info exists CHIPNAME] } {
	set _CHIPNAME $CHIPNAME
} else {
	set _CHIPNAME stm32mp21x
}

# Set to 0 to prevent CPU examine. Default examine them
if { ! [info exists EN_CA35] } {
	set EN_CA35 1
}
if { ! [info exists EN_CM33] } {
	set EN_CM33 1
}

set _ENDIAN little

# jtag scan chain
if { [info exists CPUTAPID] } {
	set _CPUTAPID $CPUTAPID
} else {
	if { [using_jtag] } {
		set _CPUTAPID 0x6ba00477
	} {
		set _CPUTAPID 0x6ba02477
	}
}

# Chip Level TAP Controller, only in jtag mode
if { [info exists CLCTAPID] } {
	set _CLCTAPID $CLCTAPID
} else {
	set _CLCTAPID 0x16503041
}

swj_newdap $_CHIPNAME tap -expected-id $_CPUTAPID -irlen 4 -ircapture 0x01 -irmask 0x0f
if { [using_jtag] } {
	swj_newdap $_CHIPNAME.clc tap -expected-id $_CLCTAPID -irlen 5
}

dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.tap

# define AXI & APB Memory Access Ports
# NOTE: do not change the order of target create
target create $_CHIPNAME.ap0 mem_ap -dap $_CHIPNAME.dap -ap-num 0
target create $_CHIPNAME.ap1 mem_ap -dap $_CHIPNAME.dap -ap-num 1
target create $_CHIPNAME.axi mem_ap -dap $_CHIPNAME.dap -ap-num 2
target create $_CHIPNAME.ap3 mem_ap -dap $_CHIPNAME.dap -ap-num 3 -defer-examine

# define the Cortex-A35
cti create $_CHIPNAME.cti.a35 -dap $_CHIPNAME.dap -ap-num 1 -baseaddr 0x80220000
target create $_CHIPNAME.a35 aarch64 -dap $_CHIPNAME.dap -ap-num 1 -dbgbase 0x80210000 \
	-cti $_CHIPNAME.cti.a35 -defer-examine

# define the Cortex-M33
target create $_CHIPNAME.m33 cortex_m -dap $_CHIPNAME.dap -ap-num 3 -defer-examine
cti create $_CHIPNAME.cti.m33 -dap $_CHIPNAME.dap -ap-num 3 -baseaddr 0xe0042000

# define the system CTIs
cti create $_CHIPNAME.cti.sys0 -dap $_CHIPNAME.dap -ap-num 1 -baseaddr 0x80080000
cti create $_CHIPNAME.cti.sys1 -dap $_CHIPNAME.dap -ap-num 1 -baseaddr 0x80090000

swo  create $_CHIPNAME.swo  -dap $_CHIPNAME.dap -ap-num 1 -baseaddr 0x800A0000
tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 1 -baseaddr 0x80040000

targets $_CHIPNAME.a35

reset_config srst_pulls_trst

adapter speed 5000
adapter srst pulse_width 200
# wait 1 seconds for bootrom
adapter srst delay 1000

# set CSW for AXI
$_CHIPNAME.dap apsel 2
$_CHIPNAME.dap apcsw 0x12800000

# mmw with target selection
proc target_mmw {target reg setbits clearbits} {
	set val [eval $target read_memory $reg 32 1]
	set val [expr {($val & ~$clearbits) | $setbits}]
	eval $target mww $reg $val
}

lappend _telnet_autocomplete_skip _enable_debug
# Uses AP0 and AXI
proc _enable_debug {} {
	# Enable DBGMCU clock in RC
	$::_CHIPNAME.axi mww 0x44200520 0x500

	# set debug enable bits in DBGMCU_CR to get ap3/cm33 visible
	$::_CHIPNAME.ap0 mww 0x80001004 0x7

	# Freeze watchdogs on CPU halt
	$::_CHIPNAME.axi mww 0x440a003c 0x00000026
	$::_CHIPNAME.axi mww 0x440a0040 0x00000038
}

lappend _telnet_autocomplete_skip _rcc_enable_traceclk
# Uses AXI
proc _rcc_enable_traceclk {} {
	# set bit TRACEEN in RCC_DBGCFGR to clock TPIU
	target_mmw $::_CHIPNAME.axi 0x44200520 0x200 0
}

lappend _telnet_autocomplete_skip _handshake_with_wrapper
# Uses AP0, AP1 and AP3
proc _handshake_with_wrapper { halt } {
	set dbgmcu_cr 0
	catch {set dbgmcu_cr [eval $::_CHIPNAME.ap0 read_memory 0x80001004 32 1]}
	if {[expr {($dbgmcu_cr & 0x07) == 0x00}]} {
		echo "\nWARNING: FSBL wrapper not detected. Board in dev boot mode?\n"
		return
	}

	if { $halt } {
		if { $::EN_CA35 } {
			$::_CHIPNAME.ap1 arp_examine
			$::_CHIPNAME.ap1 arp_halt
			$::_CHIPNAME.ap1 mww 0x80210300 0
			target_mmw $::_CHIPNAME.ap1 0x80210088 0x00004000 0
		}
		if { $::EN_CM33 } {
			$::_CHIPNAME.ap3 arp_examine
			$::_CHIPNAME.ap3 arp_halt
			$::_CHIPNAME.ap3 mww 0xe000edf0 0xa05f0001
		}
	}

	# alert wrapper that debugger is ready
	$::_CHIPNAME.ap0 mww 0x80001004 0x07
}

lappend _telnet_autocomplete_skip _enable_dbgmcu_on_devboot
# In DEV BOOT the BootROM does not completes the sequence to enable the
# visibility of DBGMCU on AP0.
# Write a value in DBGMCU_DBG_AUTH_DEV from CID1.
# Returns 1 if DEV BOOT is detected
# Uses AP2 (AXI bus)
proc _enable_dbgmcu_on_devboot {} {
	$::_CHIPNAME.axi mww 0x44230004 0
	set boot_pins [expr {[$::_CHIPNAME.axi read_memory 0x44230000 32 1] & 0xf}]
	if {$boot_pins != 0x3 && $boot_pins != 0xc} {
		return 0
	}

	set rifsc_rimc_cr [$::_CHIPNAME.axi read_memory 0x42080c00 32 1]
	if {$rifsc_rimc_cr != 0x00008710} {
		echo "RIFSC_RIMC_CR modified, skip activation of DBGMCU"
		return 1
	}

	# Enable DBGMCU clock in RC
	$::_CHIPNAME.axi mww 0x44200520 0x500

	# Change DAP (AXI) CID, write in DBGMCU, set back DAP CID
	$::_CHIPNAME.axi mww 0x42080c00 0x00008110
	$::_CHIPNAME.axi mww 0x440A0104 1
	$::_CHIPNAME.axi mww 0x42080c00 0x00008710
	return 1
}

$_CHIPNAME.m33 configure -event reset-assert { }

$_CHIPNAME.axi configure -event reset-assert-post {
	adapter assert srst
}

$_CHIPNAME.axi configure -event reset-deassert-pre {
	adapter deassert srst deassert trst
	$::_CHIPNAME.axi arp_examine
	set is_dev_boot [_enable_dbgmcu_on_devboot]
	if { !$is_dev_boot } {
		_handshake_with_wrapper $halt
	}
	_enable_debug
	_rcc_enable_traceclk
	if { $::EN_CA35 } {
		$::_CHIPNAME.a35 arp_examine
		if { $halt } {
			$::_CHIPNAME.a35 arp_halt
		}
	}
	if { $::EN_CM33 } {
		$::_CHIPNAME.ap3 arp_examine
		$::_CHIPNAME.m33 arp_examine
		if { $halt } {
			$::_CHIPNAME.ap3 arp_halt
			$::_CHIPNAME.m33 arp_halt
		}
	}
}

$_CHIPNAME.axi configure -event examine-end {
	set is_dev_boot [_enable_dbgmcu_on_devboot]
	if { $is_dev_boot } {
		echo "Dev boot detected"
	}
	_enable_debug
	_rcc_enable_traceclk
	if { $::EN_CA35 } {
		$::_CHIPNAME.a35 arp_examine
	}
	if { $::EN_CM33 } {
		$::_CHIPNAME.ap3 arp_examine
		$::_CHIPNAME.m33 arp_examine
	}
}