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https://git.code.sf.net/p/openocd/code
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f11b677dec
Align the target script to the handshake implemented in the latest version of stm32wrapper4dbg to get access to the debug port. Use hwthread with the SMP node. Allow ignoring/masking some CPU from the configuration with the variables EN_<cpu>. Change-Id: I7117dd7df20b4f6b6e28f911e3e91ee763bdd200 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/8984 Tested-by: jenkins
222 lines
6.0 KiB
INI
222 lines
6.0 KiB
INI
# SPDX-License-Identifier: GPL-2.0-or-later
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# STMicroelectronics STM32MP15x (Single/Dual Cortex-A7 plus Cortex-M4)
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# http://www.st.com/stm32mp1
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# HLA does not support multi-cores nor custom CSW nor AP other than 0
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if { [using_hla] } {
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echo "ERROR: HLA transport cannot work with this target."
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echo "ERROR: To use STLink switch to DAP mode, as in \"board/stm32mp15x_dk2.cfg\"."
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shutdown
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}
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source [find target/swj-dp.tcl]
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME stm32mp15x
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}
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# Set to 0 to prevent CPU examine. Default examine them
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if { ! [info exists EN_CA7_0] } {
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set EN_CA7_0 1
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}
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if { ! [info exists EN_CA7_1] } {
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set EN_CA7_1 1
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}
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if { ! [info exists EN_CM4] } {
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set EN_CM4 1
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}
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if { [info exists CPUTAPID] } {
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set _CPUTAPID $CPUTAPID
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} else {
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if { [using_jtag] } {
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set _CPUTAPID 0x6ba00477
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} else {
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set _CPUTAPID 0x6ba02477
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}
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}
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# Chip Level TAP Controller, only in jtag mode
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if { [info exists CLCTAPID] } {
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set _CLCTAPID $CLCTAPID
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} else {
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set _CLCTAPID 0x06500041
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}
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swj_newdap $_CHIPNAME tap -expected-id $_CPUTAPID -irlen 4
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if { [using_jtag] } {
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jtag newtap $_CHIPNAME.clc tap -expected-id $_CLCTAPID -irlen 5
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}
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dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.tap -ignore-syspwrupack
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# NOTE: keep ap-num and dbgbase to speed-up examine after reset
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# NOTE: do not change the order of target create
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target create $_CHIPNAME.ap1 mem_ap -dap $_CHIPNAME.dap -ap-num 1
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target create $_CHIPNAME.ap2 mem_ap -dap $_CHIPNAME.dap -ap-num 2
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target create $_CHIPNAME.axi mem_ap -dap $_CHIPNAME.dap -ap-num 0
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target create $_CHIPNAME.cpu0 cortex_a -dap $_CHIPNAME.dap -ap-num 1 -coreid 0 -dbgbase 0xE00D0000 -defer-examine
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target create $_CHIPNAME.cpu1 cortex_a -dap $_CHIPNAME.dap -ap-num 1 -coreid 1 -dbgbase 0xE00D2000 -defer-examine
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target create $_CHIPNAME.cm4 cortex_m -dap $_CHIPNAME.dap -ap-num 2 -defer-examine
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targets $_CHIPNAME.cpu0
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target smp $_CHIPNAME.cpu0 $_CHIPNAME.cpu1
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$_CHIPNAME.cpu0 configure -rtos hwthread
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$_CHIPNAME.cpu1 configure -rtos hwthread
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$_CHIPNAME.cpu0 cortex_a maskisr on
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$_CHIPNAME.cpu1 cortex_a maskisr on
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$_CHIPNAME.cpu0 cortex_a dacrfixup on
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$_CHIPNAME.cpu1 cortex_a dacrfixup on
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cti create $_CHIPNAME.cti.sys -dap $_CHIPNAME.dap -ap-num 1 -baseaddr 0xE0094000
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cti create $_CHIPNAME.cti.cpu0 -dap $_CHIPNAME.dap -ap-num 1 -baseaddr 0xE00D8000
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cti create $_CHIPNAME.cti.cpu1 -dap $_CHIPNAME.dap -ap-num 1 -baseaddr 0xE00D9000
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cti create $_CHIPNAME.cti.cm4 -dap $_CHIPNAME.dap -ap-num 2 -baseaddr 0xE0043000
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swo create $_CHIPNAME.swo -dap $_CHIPNAME.dap -ap-num 1 -baseaddr 0xE0083000
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tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 1 -baseaddr 0xE0093000
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# interface does not work while srst is asserted
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# this is target specific, valid for every board
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# Errata "2.3.5 Incorrect reset of glitch-free kernel clock switch" requires
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# srst to force VDDCORE power cycle or pull srst_core. Both cases reset the
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# debug unit, behavior equivalent to "srst_pulls_trst"
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reset_config srst_gates_jtag srst_pulls_trst
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adapter speed 5000
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adapter srst pulse_width 200
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# bootrom has an internal timeout of 1 second for detecting the boot flash.
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# wait at least 1 second to guarantee we are out of bootrom
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adapter srst delay 1100
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add_help_text axi_secure "Set secure mode for following AXI accesses"
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proc axi_secure {} {
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$::_CHIPNAME.dap apsel 0
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$::_CHIPNAME.dap apcsw 0x10006000
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}
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add_help_text axi_nsecure "Set non-secure mode for following AXI accesses"
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proc axi_nsecure {} {
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$::_CHIPNAME.dap apsel 0
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$::_CHIPNAME.dap apcsw 0x30006000
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}
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axi_secure
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# mmw with target selection
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proc target_mmw {target reg setbits clearbits} {
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set val [eval $target read_memory $reg 32 1]
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set val [expr {($val & ~$clearbits) | $setbits}]
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eval $target mww $reg $val
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}
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lappend _telnet_autocomplete_skip _enable_debug
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# Uses AP1
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proc _enable_debug {} {
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# set debug enable bits in DBGMCU_CR to get ap2 and cm4 visible
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catch {$::_CHIPNAME.ap1 mww 0xe0081004 0x00000007}
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# freeze watchdog 1 and 2 on cores halted
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catch {$::_CHIPNAME.ap1 mww 0xe008102c 0x00000004}
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catch {$::_CHIPNAME.ap1 mww 0xe008104c 0x00000008}
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}
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lappend _telnet_autocomplete_skip _handshake_with_wrapper
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# Uses AP1
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proc _handshake_with_wrapper { halt } {
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set dbgmcu_cr 0
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catch {set dbgmcu_cr [eval $::_CHIPNAME.ap1 read_memory 0xe0081004 32 1]}
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if {[expr {($dbgmcu_cr & 0x07) == 0x00}]} {
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echo "\nWARNING: FSBL wrapper not detected. Board in dev boot mode?\n"
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return
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}
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if { $halt } {
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$::_CHIPNAME.ap1 arp_halt
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if { $::EN_CA7_0 } {
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$::_CHIPNAME.ap1 arp_halt
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$::_CHIPNAME.ap1 mww 0xe00d0300 0
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target_mmw $::_CHIPNAME.ap1 0xe00d0088 0x00004000 0
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}
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}
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$::_CHIPNAME.ap1 mww 0xe0081004 0x7
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}
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lappend _telnet_autocomplete_skip _detect_cpu1
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# Uses AP1
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proc _detect_cpu1 {} {
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if { !$::EN_CA7_1 } {
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return
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}
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set cpu1_prsr [$::_CHIPNAME.ap1 read_memory 0xE00D2314 32 1]
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set dual_core [expr {$cpu1_prsr & 1}]
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if { !$dual_core } {
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set ::EN_CA7_1 0
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}
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}
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lappend _telnet_autocomplete_skip _rcc_enable_traceclk
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proc _rcc_enable_traceclk {} {
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$::_CHIPNAME.ap2 mww 0x5000080c 0x301
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}
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# FIXME: most of handler below will be removed once reset framework get merged
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$_CHIPNAME.cm4 configure -event reset-assert { }
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$_CHIPNAME.ap1 configure -event reset-assert-post {
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adapter assert srst
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}
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$_CHIPNAME.ap1 configure -event reset-deassert-pre {
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adapter deassert srst deassert trst
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$::_CHIPNAME.ap1 arp_examine
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_handshake_with_wrapper $halt
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if { $::EN_CA7_0 } {
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$::_CHIPNAME.cpu0 arp_examine
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if { $halt } {
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$::_CHIPNAME.cpu0 arp_halt
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}
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}
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if { $::EN_CA7_1 } {
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$::_CHIPNAME.cpu1 arp_examine
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if { $halt } {
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$::_CHIPNAME.cpu1 arp_halt
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}
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}
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_enable_debug
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}
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$_CHIPNAME.ap2 configure -event reset-deassert-pre {
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_rcc_enable_traceclk
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if { $::EN_CM4 } {
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$::_CHIPNAME.cm4 arp_examine
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if { $halt } {
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$::_CHIPNAME.cm4 arp_halt
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}
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}
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}
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$_CHIPNAME.ap1 configure -event examine-end {
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_enable_debug
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_detect_cpu1
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if { $::EN_CA7_0 } {
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$::_CHIPNAME.cpu0 arp_examine
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}
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if { $::EN_CA7_1 } {
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$::_CHIPNAME.cpu1 arp_examine
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}
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}
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$_CHIPNAME.ap2 configure -event examine-end {
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_rcc_enable_traceclk
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if { $::EN_CM4 } {
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$::_CHIPNAME.cm4 arp_examine
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}
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}
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