mirror of
https://git.code.sf.net/p/openocd/code
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e6505b0489
For historical reasons, no license information was added to the
tcl files. This makes trivial adding the SPDX tag through script:
fgrep -rL SPDX tcl/ target| while read a;do \
sed -i '1{i# SPDX-License-Identifier: GPL-2.0-or-later\n
}' $a;done
With no specific license information from the author, let's extend
the OpenOCD project license GPL-2.0-or-later to the files.
Change-Id: I7b2610300b24cccd07bfa6fb5f1266970d5d3a1b
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7027
Tested-by: jenkins
157 lines
4.1 KiB
INI
157 lines
4.1 KiB
INI
# SPDX-License-Identifier: GPL-2.0-or-later
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# The QCA4531 is a two stream (2x2) 802.11b/g/n single-band programmable
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# Wi-Fi System-on-Chip (SoC) for the Internet of Things (IoT).
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#
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# Product page:
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# https://www.qualcomm.com/products/qca4531
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#
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# Notes:
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# - MIPS Processor ID (PRId): 0x00019374
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# - 24Kc MIPS processor with 64 KB I-Cache and 32 KB D-Cache,
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# operating at up to 650 MHz
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# - External 16-bit DDR1, operating at up to 200 MHz, DDR2 operating at up
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# to 300 MHz
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# - TRST is not available.
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# - EJTAG PrRst signal is not supported
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# - RESET_L pin B56 on the SoC will reset internal JTAG logic.
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#
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# Pins related for debug and bootstrap:
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# Name Pin Description
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# JTAG
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# JTAG_TCK GPIO0, (A27) Software configurable, default JTAG
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# JTAG_TDI GPIO1, (B23) Software configurable, default JTAG
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# JTAG_TDO GPIO2, (A28) Software configurable, default JTAG
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# JTAG_TMS GPIO3, (A29) Software configurable, default JTAG
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# Reset
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# RESET_L -, (B56) Input only
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# SYS_RST_L GPIO17, (A79) Output reset request or GPIO
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# Bootstrap
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# JTAG_MODE GPIO16, (A78) 0 - JTAG (Default); 1 - EJTAG
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# DDR_SELECT GPIO10, (A57) 0 - DDR2; 1 - DDR1
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# UART
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# UART0_SOUT GPIO10, (A57)
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# UART0_SIN GPIO9, (B49)
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# Per default we need to use "none" variant to be able properly "reset init"
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# or "reset halt" the CPU.
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reset_config none srst_pulls_trst
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# For SRST based variant we still need proper timings.
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# For ETH part the reset should be asserted at least for 10ms
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# Since there is no other information let's take 100ms to be sure.
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adapter srst pulse_width 100
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# according to the SoC documentation it should take at least 5ms from
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# reset end till bootstrap end. In the practice we need 8ms to get JTAG back
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# to live.
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adapter srst delay 8
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $_CHIPNAME
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} else {
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set _CHIPNAME qca4531
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}
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jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x00000001
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set _TARGETNAME $_CHIPNAME.cpu
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target create $_TARGETNAME mips_m4k -endian big -chain-position $_TARGETNAME
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# provide watchdog helper.
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proc disable_watchdog { } {
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mww 0xb8060008 0x0
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}
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$_TARGETNAME configure -event halted { disable_watchdog }
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# Since PrRst is not supported and SRST will reset complete chip
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# with JTAG engine, we need to reset CPU from CPU itself.
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$_TARGETNAME configure -event reset-assert-pre {
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halt
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}
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$_TARGETNAME configure -event reset-assert {
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catch "mww 0xb806001C 0x01000000"
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}
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# To be able to trigger complete chip reset, in case JTAG is blocked
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# or CPU not responding, we still can use this helper.
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proc full_reset { } {
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reset_config srst_only
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reset
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halt
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reset_config none
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}
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# Section with helpers which can be used by boards
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proc qca4531_ddr2_550_550_init {} {
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# Clear reset flags for different SoC components
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mww 0xb806001c 0xfeceffff
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mww 0xb806001c 0xeeceffff
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mww 0xb806001c 0xe6ceffff
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# PMU configurations
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# Internal Switcher
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mww 0xb8116c40 0x633c8176
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# Increase the DDR voltage
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mww 0xb8116c44 0x10200000
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# XTAL Configurations
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mww 0xb81162c0 0x4b962100
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mww 0xb81162c4 0x480
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mww 0xb81162c8 0x04000144
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# Recommended PLL configurations
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mww 0xb81161c4 0x54086000
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mww 0xb8116244 0x54086000
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# PLL init
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mww 0xb8050008 0x0131001c
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mww 0xb8050000 0x40001580
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mww 0xb8050004 0x40015800
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mww 0xb8050008 0x0131001c
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mww 0xb8050000 0x00001580
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mww 0xb8050004 0x00015800
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mww 0xb8050008 0x01310000
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mww 0xb8050044 0x781003ff
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mww 0xb8050048 0x003c103f
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# DDR2 init
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mww 0xb8000108 0x401f0042
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mww 0xb80000b8 0x0000166d
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mww 0xb8000000 0xcfaaf33b
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mww 0xb800015c 0x0000000f
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mww 0xb8000004 0xa272efa8
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mww 0xb8000018 0x0000ffff
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mww 0xb80000c4 0x74444444
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mww 0xb80000c8 0x00000444
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mww 0xb8000004 0xa210ee28
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mww 0xb8000004 0xa2b2e1a8
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mww 0xb8000010 0x8
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mww 0xb80000bc 0x0
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mww 0xb8000010 0x10
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mww 0xb80000c0 0x0
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mww 0xb8000010 0x40
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mww 0xb800000c 0x2
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mww 0xb8000010 0x2
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mww 0xb8000008 0xb43
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mww 0xb8000010 0x1
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mww 0xb8000010 0x8
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mww 0xb8000010 0x4
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mww 0xb8000010 0x4
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mww 0xb8000008 0xa43
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mww 0xb8000010 0x1
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mww 0xb800000c 0x382
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mww 0xb8000010 0x2
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mww 0xb800000c 0x402
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mww 0xb8000010 0x2
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mww 0xb8000014 0x40be
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mww 0xb800001C 0x20
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mww 0xb8000020 0x20
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mww 0xb80000cc 0xfffff
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# UART GPIO programming
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mww 0xb8040000 0xff30b
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mww 0xb8040044 0x908
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mww 0xb8040034 0x160000
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}
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