mirror of
https://git.code.sf.net/p/openocd/code
synced 2024-11-14 18:37:11 +00:00
19ef6634f0
After 'reset run' or 'reset halt' the loaded application is expected to manipulate RAMON register to workaround the known silicon errata. Moreover, writing to RAMON register from 'reset-end' event after 'reset run' may collide with application intentions. Use the workaround in 'reset-init' event only to ensure correct function of target algorithms. Change-Id: I7d2d92e6805a05a83676edb46b3163ef39b9a7e4 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: https://review.openocd.org/c/openocd/+/8104 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
62 lines
1.6 KiB
INI
62 lines
1.6 KiB
INI
# SPDX-License-Identifier: GPL-2.0-or-later
|
|
|
|
#
|
|
# script for Nordic nRF51 series, a Cortex-M0 chip
|
|
#
|
|
|
|
source [find target/swj-dp.tcl]
|
|
|
|
if { [info exists CHIPNAME] } {
|
|
set _CHIPNAME $CHIPNAME
|
|
} else {
|
|
set _CHIPNAME nrf51
|
|
}
|
|
|
|
if { [info exists ENDIAN] } {
|
|
set _ENDIAN $ENDIAN
|
|
} else {
|
|
set _ENDIAN little
|
|
}
|
|
|
|
# Work-area is a space in RAM used for flash programming
|
|
# By default use 16kB
|
|
if { [info exists WORKAREASIZE] } {
|
|
set _WORKAREASIZE $WORKAREASIZE
|
|
} else {
|
|
set _WORKAREASIZE 0x4000
|
|
}
|
|
|
|
if { [info exists CPUTAPID] } {
|
|
set _CPUTAPID $CPUTAPID
|
|
} else {
|
|
set _CPUTAPID 0x0bb11477
|
|
}
|
|
|
|
swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID
|
|
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
|
|
|
|
set _TARGETNAME $_CHIPNAME.cpu
|
|
target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
|
|
|
|
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
|
|
|
|
if {![using_hla]} {
|
|
# The chip supports standard ARM/Cortex-M0 SYSRESETREQ signal
|
|
cortex_m reset_config sysresetreq
|
|
}
|
|
|
|
flash bank $_CHIPNAME.flash nrf5 0x00000000 0 0 0 $_TARGETNAME
|
|
flash bank $_CHIPNAME.uicr nrf5 0x10001000 0 0 0 $_TARGETNAME
|
|
|
|
# The chip should start up from internal 16Mhz RC, so setting adapter
|
|
# clock to 1Mhz should be OK
|
|
adapter speed 1000
|
|
|
|
proc enable_all_ram {} {
|
|
# nRF51822 Product Anomaly Notice (PAN) #16 explains that not all RAM banks
|
|
# are reliably enabled after reset on some revisions (contrary to spec.) So after
|
|
# resetting we enable all banks via the RAMON register
|
|
mww 0x40000524 0xF
|
|
}
|
|
$_TARGETNAME configure -event reset-init { enable_all_ram }
|