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https://git.code.sf.net/p/openocd/code
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152becc460
Move target configuration files into a dedicated vendor directory as required by the new guideline for configuration files. Note that the moved files are still accessible via the old path to ensure backwards compatibility. This works because of the extended file search in vendor folders. Change-Id: If3935985769dc543e8c7d72cda590c9d79303abb Signed-off-by: Marc Schink <dev@zapb.de> Reviewed-on: https://review.openocd.org/c/openocd/+/8905 Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Tested-by: jenkins
62 lines
1.6 KiB
INI
62 lines
1.6 KiB
INI
# SPDX-License-Identifier: GPL-2.0-or-later
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#
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# script for Nordic nRF51 series, a Cortex-M0 chip
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#
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source [find target/swj-dp.tcl]
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME nrf51
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}
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if { [info exists ENDIAN] } {
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set _ENDIAN $ENDIAN
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} else {
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set _ENDIAN little
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}
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# Work-area is a space in RAM used for flash programming
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# By default use 16kB
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if { [info exists WORKAREASIZE] } {
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set _WORKAREASIZE $WORKAREASIZE
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} else {
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set _WORKAREASIZE 0x4000
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}
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if { [info exists CPUTAPID] } {
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set _CPUTAPID $CPUTAPID
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} else {
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set _CPUTAPID 0x0bb11477
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}
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swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID
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dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
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set _TARGETNAME $_CHIPNAME.cpu
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target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
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$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
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if {![using_hla]} {
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# The chip supports standard ARM/Cortex-M0 SYSRESETREQ signal
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cortex_m reset_config sysresetreq
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}
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flash bank $_CHIPNAME.flash nrf5 0x00000000 0 0 0 $_TARGETNAME
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flash bank $_CHIPNAME.uicr nrf5 0x10001000 0 0 0 $_TARGETNAME
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# The chip should start up from internal 16Mhz RC, so setting adapter
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# clock to 1Mhz should be OK
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adapter speed 1000
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proc enable_all_ram {} {
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# nRF51822 Product Anomaly Notice (PAN) #16 explains that not all RAM banks
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# are reliably enabled after reset on some revisions (contrary to spec.) So after
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# resetting we enable all banks via the RAMON register
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mww 0x40000524 0xF
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}
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$_TARGETNAME configure -event reset-init { enable_all_ram }
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