mirror of
https://git.code.sf.net/p/openocd/code
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e6505b0489
For historical reasons, no license information was added to the
tcl files. This makes trivial adding the SPDX tag through script:
fgrep -rL SPDX tcl/ target| while read a;do \
sed -i '1{i# SPDX-License-Identifier: GPL-2.0-or-later\n
}' $a;done
With no specific license information from the author, let's extend
the OpenOCD project license GPL-2.0-or-later to the files.
Change-Id: I7b2610300b24cccd07bfa6fb5f1266970d5d3a1b
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7027
Tested-by: jenkins
97 lines
2.7 KiB
INI
97 lines
2.7 KiB
INI
# SPDX-License-Identifier: GPL-2.0-or-later
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#
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# Support for General Plus GP326XXXA chips
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#
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME gp326xxxa
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}
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if { [info exists ENDIAN] } {
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set _ENDIAN $ENDIAN
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} else {
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set _ENDIAN little
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}
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if { [info exists CPUTAPID] } {
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set _CPUTAPID $CPUTAPID
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} else {
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set _CPUTAPID 0x4f1f0f0f
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}
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jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
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set _TARGETNAME $_CHIPNAME.cpu
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target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME
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# Use internal SRAM as a work area
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$_TARGETNAME configure -work-area-phys 0xf8000000 -work-area-size 0x8000 -work-area-backup 0
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# The chip has both lines connected together
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reset_config trst_and_srst srst_pulls_trst
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# This delay is needed otherwise communication with the target would
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# be unreliable
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adapter srst delay 100
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# Set the adapter speed ridiculously low just in case we are
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# running off of a 32kHz clock
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adapter speed 2
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proc gp32xxxa_halt_and_reset_control_registers {} {
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# System control registers
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set P_SYSTEM_CTRL_NEW 0xD0000008
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set P_SYSTEM_CTRL 0xD000000C
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set P_SYSTEM_CLK_EN0 0xD0000010
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set P_SYSTEM_CLK_EN1 0xD0000014
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set P_SYSTEM_RESET_FLAG 0xD0000018
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set P_SYSTEM_CLK_CTRL 0xD000001C
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set P_SYSTEM_LVR_CTRL 0xD0000020
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set P_SYSTEM_WATCHDOG_CTRL 0xD0000024
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set P_SYSTEM_PLLEN 0xD000005C
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# Since we can't use SRST without pulling TRST
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# we can't assume the state of the clock configuration
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# or watchdog settings. So reset them before porceeding
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# Set the adapter speed ridiculously low just in case we are
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# running off of a 32kHz clock
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adapter speed 2
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# Disable any advanced features at this stage
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arm7_9 dcc_downloads disable
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arm7_9 fast_memory_access disable
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# Do a "soft reset"
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soft_reset_halt
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# Reset all system control registers to their default "after-reset" values
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mwh $P_SYSTEM_WATCHDOG_CTRL 0x0000
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mwh $P_SYSTEM_LVR_CTRL 0x0000
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mwh $P_SYSTEM_CTRL_NEW 0x0001
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mwh $P_SYSTEM_CTRL 0x0001
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# Clear all reset flags by writing 1's
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mwh $P_SYSTEM_RESET_FLAG 0x001C
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mwh $P_SYSTEM_CLK_CTRL 0x8000
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mwh $P_SYSTEM_CLK_EN0 0xFFFF
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mwh $P_SYSTEM_CLK_EN1 0xFFFF
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mwh $P_SYSTEM_PLLEN 0x0010
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# Unfortunately there's no register that would allow us to
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# know if PLL is locked. So just wait for 100ms in hopes that
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# it would be enough.
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sleep 100
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# Now that we know that we are running at 48Mhz
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# Increase JTAG speed and enable speed optimization features
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adapter speed 5000
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arm7_9 dcc_downloads enable
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arm7_9 fast_memory_access enable
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}
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$_TARGETNAME configure -event reset-end { gp32xxxa_halt_and_reset_control_registers }
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