mirror of
https://git.code.sf.net/p/openocd/code
synced 2024-11-14 18:37:11 +00:00
e6505b0489
For historical reasons, no license information was added to the
tcl files. This makes trivial adding the SPDX tag through script:
fgrep -rL SPDX tcl/ target| while read a;do \
sed -i '1{i# SPDX-License-Identifier: GPL-2.0-or-later\n
}' $a;done
With no specific license information from the author, let's extend
the OpenOCD project license GPL-2.0-or-later to the files.
Change-Id: I7b2610300b24cccd07bfa6fb5f1266970d5d3a1b
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7027
Tested-by: jenkins
380 lines
11 KiB
INI
380 lines
11 KiB
INI
# SPDX-License-Identifier: GPL-2.0-or-later
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#
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# Utility code for DaVinci-family chips
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#
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# davinci_pinmux: assigns PINMUX$reg <== $value
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proc davinci_pinmux {soc reg value} {
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mww [expr {[dict get $soc sysbase] + 4 * $reg}] $value
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}
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source [find mem_helper.tcl]
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#
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# pll_setup: initialize PLL
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# - pll_addr ... physical addr of controller
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# - mult ... pll multiplier
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# - config ... dict mapping { prediv, postdiv, div[1-9] } to dividers
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#
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# For PLLs that don't have a given register (e.g. plldiv8), or where a
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# given divider is non-programmable, caller provides *NO* config mapping.
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#
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# PLL version 0x02: tested on dm355
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# REVISIT: On dm6446/dm357 the PLLRST polarity is different.
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proc pll_v02_setup {pll_addr mult config} {
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set pll_ctrl_addr [expr {$pll_addr + 0x100}]
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set pll_ctrl [mrw $pll_ctrl_addr]
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# 1 - clear CLKMODE (bit 8) iff using on-chip oscillator
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# NOTE: this assumes we should clear that bit
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set pll_ctrl [expr {$pll_ctrl & ~0x0100}]
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mww $pll_ctrl_addr $pll_ctrl
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# 2 - clear PLLENSRC (bit 5)
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set pll_ctrl [expr {$pll_ctrl & ~0x0020}]
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mww $pll_ctrl_addr $pll_ctrl
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# 3 - clear PLLEN (bit 0) ... enter bypass mode
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set pll_ctrl [expr {$pll_ctrl & ~0x0001}]
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mww $pll_ctrl_addr $pll_ctrl
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# 4 - wait at least 4 refclk cycles
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sleep 1
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# 5 - set PLLRST (bit 3)
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set pll_ctrl [expr {$pll_ctrl | 0x0008}]
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mww $pll_ctrl_addr $pll_ctrl
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# 6 - set PLLDIS (bit 4)
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set pll_ctrl [expr {$pll_ctrl | 0x0010}]
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mww $pll_ctrl_addr $pll_ctrl
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# 7 - clear PLLPWRDN (bit 1)
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set pll_ctrl [expr {$pll_ctrl & ~0x0002}]
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mww $pll_ctrl_addr $pll_ctrl
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# 8 - clear PLLDIS (bit 4)
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set pll_ctrl [expr {$pll_ctrl & ~0x0010}]
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mww $pll_ctrl_addr $pll_ctrl
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# 9 - optional: write prediv, postdiv, and pllm
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# NOTE: for dm355 PLL1, postdiv is controlled via MISC register
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mww [expr {$pll_addr + 0x0110}] [expr {($mult - 1) & 0xff}]
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if { [dict exists $config prediv] } {
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set div [dict get $config prediv]
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set div [expr {0x8000 | ($div - 1)}]
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mww [expr {$pll_addr + 0x0114}] $div
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}
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if { [dict exists $config postdiv] } {
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set div [dict get $config postdiv]
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set div [expr {0x8000 | ($div - 1)}]
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mww [expr {$pll_addr + 0x0128}] $div
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}
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# 10 - optional: set plldiv1, plldiv2, ...
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# NOTE: this assumes some registers have their just-reset values:
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# - PLLSTAT.GOSTAT is clear when we enter
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# - ALNCTL has everything set
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set go 0
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if { [dict exists $config div1] } {
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set div [dict get $config div1]
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set div [expr {0x8000 | ($div - 1)}]
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mww [expr {$pll_addr + 0x0118}] $div
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set go 1
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}
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if { [dict exists $config div2] } {
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set div [dict get $config div2]
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set div [expr {0x8000 | ($div - 1)}]
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mww [expr {$pll_addr + 0x011c}] $div
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set go 1
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}
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if { [dict exists $config div3] } {
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set div [dict get $config div3]
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set div [expr {0x8000 | ($div - 1)}]
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mww [expr {$pll_addr + 0x0120}] $div
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set go 1
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}
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if { [dict exists $config div4] } {
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set div [dict get $config div4]
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set div [expr {0x8000 | ($div - 1)}]
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mww [expr {$pll_addr + 0x0160}] $div
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set go 1
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}
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if { [dict exists $config div5] } {
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set div [dict get $config div5]
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set div [expr {0x8000 | ($div - 1)}]
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mww [expr {$pll_addr + 0x0164}] $div
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set go 1
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}
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if {$go != 0} {
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# write pllcmd.GO; poll pllstat.GO
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mww [expr {$pll_addr + 0x0138}] 0x01
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set pllstat [expr {$pll_addr + 0x013c}]
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while {[expr {[mrw $pllstat] & 0x01}] != 0} { sleep 1 }
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}
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mww [expr {$pll_addr + 0x0138}] 0x00
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# 11 - wait at least 5 usec for reset to finish
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# (assume covered by overheads including JTAG messaging)
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# 12 - clear PLLRST (bit 3)
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set pll_ctrl [expr {$pll_ctrl & ~0x0008}]
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mww $pll_ctrl_addr $pll_ctrl
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# 13 - wait at least 8000 refclk cycles for PLL to lock
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# if we assume 24 MHz (slowest osc), that's 1/3 msec
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sleep 3
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# 14 - set PLLEN (bit 0) ... leave bypass mode
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set pll_ctrl [expr {$pll_ctrl | 0x0001}]
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mww $pll_ctrl_addr $pll_ctrl
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}
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# PLL version 0x03: tested on dm365
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proc pll_v03_setup {pll_addr mult config} {
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set pll_ctrl_addr [expr {$pll_addr + 0x100}]
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set pll_secctrl_addr [expr {$pll_addr + 0x108}]
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set pll_ctrl [mrw $pll_ctrl_addr]
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# 1 - power up the PLL
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set pll_ctrl [expr {$pll_ctrl & ~0x0002}]
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mww $pll_ctrl_addr $pll_ctrl
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# 2 - clear PLLENSRC (bit 5)
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set pll_ctrl [expr {$pll_ctrl & ~0x0020}]
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mww $pll_ctrl_addr $pll_ctrl
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# 2 - clear PLLEN (bit 0) ... enter bypass mode
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set pll_ctrl [expr {$pll_ctrl & ~0x0001}]
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mww $pll_ctrl_addr $pll_ctrl
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# 3 - wait at least 4 refclk cycles
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sleep 1
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# 4 - set PLLRST (bit 3)
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set pll_ctrl [expr {$pll_ctrl | 0x0008}]
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mww $pll_ctrl_addr $pll_ctrl
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# 5 - wait at least 5 usec
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sleep 1
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# 6 - clear PLLRST (bit 3)
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set pll_ctrl [expr {$pll_ctrl & ~0x0008}]
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mww $pll_ctrl_addr $pll_ctrl
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# 9 - optional: write prediv, postdiv, and pllm
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mww [expr {$pll_addr + 0x0110}] [expr {($mult / 2) & 0x1ff}]
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if { [dict exists $config prediv] } {
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set div [dict get $config prediv]
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set div [expr {0x8000 | ($div - 1)}]
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mww [expr {$pll_addr + 0x0114}] $div
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}
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if { [dict exists $config postdiv] } {
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set div [dict get $config postdiv]
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set div [expr {0x8000 | ($div - 1)}]
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mww [expr {$pll_addr + 0x0128}] $div
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}
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# 10 - write start sequence to PLLSECCTL
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mww $pll_secctrl_addr 0x00470000
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mww $pll_secctrl_addr 0x00460000
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mww $pll_secctrl_addr 0x00400000
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mww $pll_secctrl_addr 0x00410000
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# 11 - optional: set plldiv1, plldiv2, ...
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# NOTE: this assumes some registers have their just-reset values:
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# - PLLSTAT.GOSTAT is clear when we enter
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set aln 0
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if { [dict exists $config div1] } {
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set div [dict get $config div1]
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set div [expr {0x8000 | ($div - 1)}]
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mww [expr {$pll_addr + 0x0118}] $div
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set aln [expr {$aln | 0x1}]
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} else {
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mww [expr {$pll_addr + 0x0118}] 0
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}
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if { [dict exists $config div2] } {
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set div [dict get $config div2]
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set div [expr {0x8000 | ($div - 1)}]
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mww [expr {$pll_addr + 0x011c}] $div
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set aln [expr {$aln | 0x2}]
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} else {
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mww [expr {$pll_addr + 0x011c}] 0
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}
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if { [dict exists $config div3] } {
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set div [dict get $config div3]
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set div [expr {0x8000 | ($div - 1)}]
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mww [expr {$pll_addr + 0x0120}] $div
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set aln [expr {$aln | 0x4}]
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} else {
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mww [expr {$pll_addr + 0x0120}] 0
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}
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if { [dict exists $config oscdiv] } {
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set div [dict get $config oscdiv]
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set div [expr {0x8000 | ($div - 1)}]
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mww [expr {$pll_addr + 0x0124}] $div
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} else {
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mww [expr {$pll_addr + 0x0124}] 0
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}
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if { [dict exists $config div4] } {
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set div [dict get $config div4]
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set div [expr {0x8000 | ($div - 1)}]
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mww [expr {$pll_addr + 0x0160}] $div
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set aln [expr {$aln | 0x8}]
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} else {
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mww [expr {$pll_addr + 0x0160}] 0
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}
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if { [dict exists $config div5] } {
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set div [dict get $config div5]
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set div [expr {0x8000 | ($div - 1)}]
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mww [expr {$pll_addr + 0x0164}] $div
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set aln [expr {$aln | 0x10}]
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} else {
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mww [expr {$pll_addr + 0x0164}] 0
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}
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if { [dict exists $config div6] } {
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set div [dict get $config div6]
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set div [expr {0x8000 | ($div - 1)}]
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mww [expr {$pll_addr + 0x0168}] $div
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set aln [expr {$aln | 0x20}]
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} else {
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mww [expr {$pll_addr + 0x0168}] 0
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}
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if { [dict exists $config div7] } {
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set div [dict get $config div7]
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set div [expr {0x8000 | ($div - 1)}]
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mww [expr {$pll_addr + 0x016c}] $div
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set aln [expr {$aln | 0x40}]
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} else {
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mww [expr {$pll_addr + 0x016c}] 0
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}
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if { [dict exists $config div8] } {
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set div [dict get $config div8]
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set div [expr {0x8000 | ($div - 1)}]
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mww [expr {$pll_addr + 0x0170}] $div
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set aln [expr {$aln | 0x80}]
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} else {
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mww [expr {$pll_addr + 0x0170}] 0
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}
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if { [dict exists $config div9] } {
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set div [dict get $config div9]
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set div [expr {0x8000 | ($div - 1)}]
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mww [expr {$pll_addr + 0x0174}] $div
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set aln [expr {$aln | 0x100}]
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} else {
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mww [expr {$pll_addr + 0x0174}] 0
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}
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if {$aln != 0} {
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# clear pllcmd.GO
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mww [expr {$pll_addr + 0x0138}] 0x00
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# write alignment flags
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mww [expr {$pll_addr + 0x0140}] $aln
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# write pllcmd.GO; poll pllstat.GO
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mww [expr {$pll_addr + 0x0138}] 0x01
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set pllstat [expr {$pll_addr + 0x013c}]
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while {[expr {[mrw $pllstat] & 0x01}] != 0} { sleep 1 }
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}
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mww [expr {$pll_addr + 0x0138}] 0x00
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set addr [dict get $config ctladdr]
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while {[expr {[mrw $addr] & 0x0e000000}] != 0x0e000000} { sleep 1 }
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# 12 - set PLLEN (bit 0) ... leave bypass mode
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set pll_ctrl [expr {$pll_ctrl | 0x0001}]
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mww $pll_ctrl_addr $pll_ctrl
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}
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# NOTE: dm6446 requires EMURSTIE set in MDCTL before certain
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# modules can be enabled.
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# prepare a non-DSP module to be enabled; finish with psc_go
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proc psc_enable {module} {
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set psc_addr 0x01c41000
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# write MDCTL
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mmw [expr {$psc_addr + 0x0a00 + (4 * $module)}] 0x03 0x1f
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}
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# prepare a non-DSP module to be reset; finish with psc_go
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proc psc_reset {module} {
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set psc_addr 0x01c41000
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# write MDCTL
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mmw [expr {$psc_addr + 0x0a00 + (4 * $module)}] 0x01 0x1f
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}
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# execute non-DSP PSC transition(s) set up by psc_enable, psc_reset, etc
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proc psc_go {} {
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set psc_addr 0x01c41000
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set ptstat_addr [expr {$psc_addr + 0x0128}]
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# just in case PTSTAT.go isn't clear
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while { [expr {[mrw $ptstat_addr] & 0x01}] != 0 } { sleep 1 }
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# write PTCMD.go ... ignoring any DSP power domain
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mww [expr {$psc_addr + 0x0120}] 1
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# wait for PTSTAT.go to clear (again ignoring DSP power domain)
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while { [expr {[mrw $ptstat_addr] & 0x01}] != 0 } { sleep 1 }
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}
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#
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# A reset using only SRST is a "Warm Reset", resetting everything in the
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# chip except ARM emulation (and everything _outside_ the chip that hooks
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# up to SRST). But many boards don't expose SRST via their JTAG connectors
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# (it's not present on TI-14 headers).
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#
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# From the chip-only perspective, a "Max Reset" is a "Warm" reset ... except
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# without any board-wide side effects, since it's triggered using JTAG using
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# either (a) ARM watchdog timer, or (b) ICEpick.
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#
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proc davinci_wdog_reset {} {
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set timer2_phys 0x01c21c00
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# NOTE -- on entry
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# - JTAG communication with the ARM *must* be working OK; this
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# may imply using adaptive clocking or disabling WFI-in-idle
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# - current target must be the DaVinci ARM
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# - that ARM core must be halted
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# - timer2 clock is still enabled (PSC 29 on most chips)
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#
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# Part I -- run regardless of being halted via JTAG
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#
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# NOTE: for now, we assume there's no DSP that could control the
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# watchdog; or, equivalently, SUSPSRC.TMR2SRC says the watchdog
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# suspend signal is controlled via ARM emulation suspend.
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#
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# EMUMGT_CLKSPEED: write FREE bit to run despite emulation halt
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mww phys [expr {$timer2_phys + 0x28}] 0x00004000
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#
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# Part II -- in case watchdog hasn't been set up
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#
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# TCR: disable, force internal clock source
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mww phys [expr {$timer2_phys + 0x20}] 0
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# TGCR: reset, force to 64-bit wdog mode, un-reset ("initial" state)
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mww phys [expr {$timer2_phys + 0x24}] 0
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mww phys [expr {$timer2_phys + 0x24}] 0x110b
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# clear counter (TIM12, TIM34) and period (PRD12, PRD34) registers
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# so watchdog triggers ASAP
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mww phys [expr {$timer2_phys + 0x10}] 0
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mww phys [expr {$timer2_phys + 0x14}] 0
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mww phys [expr {$timer2_phys + 0x18}] 0
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mww phys [expr {$timer2_phys + 0x1c}] 0
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# WDTCR: put into pre-active state, then active
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mww phys [expr {$timer2_phys + 0x28}] 0xa5c64000
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mww phys [expr {$timer2_phys + 0x28}] 0xda7e4000
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#
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# Part III -- it's ready to rumble
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#
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# WDTCR: write invalid WDKEY to trigger reset
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mww phys [expr {$timer2_phys + 0x28}] 0x00004000
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}
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