mirror of
https://git.code.sf.net/p/openocd/code
synced 2024-11-14 18:37:11 +00:00
223e3d8fe7
Fixes: 64d89d5ee1a5 ("tcl: [3/3] prepare for jimtcl 0.81 'expr' syntax change")
These syntax errors were caught by tclint v0.2.5
(https://github.com/nmoroze/tclint):
```
tclint tcl/target/c100helper.tcl | grep "syntax error"
```
Change-Id: I511c54353c4853560adca6b4852d48df2aade283
Signed-off-by: Noah Moroze <noahmoroze@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8280
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
506 lines
22 KiB
Tcl
506 lines
22 KiB
Tcl
# SPDX-License-Identifier: GPL-2.0-or-later
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proc helpC100 {} {
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echo "List of useful functions for C100 processor:"
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echo "1) reset init: will set up your Telo board"
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echo "2) setupNOR: will setup NOR access"
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echo "3) showNOR: will show current NOR config registers for 16-bit, 16MB NOR"
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echo "4) setupGPIO: will setup GPIOs for Telo board"
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echo "5) showGPIO: will show current GPIO config registers"
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echo "6) highGPIO5: will set GPIO5=NOR_addr22=1 to access upper 8MB"
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echo "7) lowGPIO5: will set GPIO5=NOR_addr22=0 to access lower 8MB"
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echo "8) showAmbaClk: will show current config registers for Amba Bus Clock"
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echo "9) setupAmbaClk: will setup Amba Bus Clock=165MHz"
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echo "10) showArmClk: will show current config registers for Arm Bus Clock"
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echo "11) setupArmClk: will setup Amba Bus Clock=450MHz"
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echo "12) ooma_board_detect: will show which version of Telo you have"
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echo "13) setupDDR2: will configure DDR2 controller, you must have PLLs configured"
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echo "14) showDDR2: will show DDR2 config registers"
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echo "15) showWatchdog: will show current register config for watchdog"
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echo "16) reboot: will trigger watchdog and reboot Telo (hw reset)"
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echo "17) bootNOR: will boot Telo from NOR"
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echo "18) setupUART0: will configure UART0 for 115200 8N1, PLLs have to be configured"
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echo "19) putcUART0: will print a character on UART0"
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echo "20) putsUART0: will print a string on UART0"
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echo "21) trainDDR2: will run DDR2 training program"
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echo "22) flashUBOOT: will program NOR sectors 0-3 with u-boot.bin"
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}
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source [find mem_helper.tcl]
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# read a 64-bit register (memory mapped)
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proc mr64bit {reg} {
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return [read_memory $reg 32 2]
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}
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# write a 64-bit register (memory mapped)
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proc mw64bit {reg value} {
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set high [expr {$value >> 32}]
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set low [expr {$value & 0xffffffff}]
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#echo [format "mw64bit(0x%x): 0x%08x%08x" $reg $high $low]
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mww $reg $low
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mww [expr {$reg+4}] $high
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}
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proc showNOR {} {
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echo "This is the current NOR setup"
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set EX_CSEN_REG [regs EX_CSEN_REG ]
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set EX_CS0_SEG_REG [regs EX_CS0_SEG_REG ]
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set EX_CS0_CFG_REG [regs EX_CS0_CFG_REG ]
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set EX_CS0_TMG1_REG [regs EX_CS0_TMG1_REG ]
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set EX_CS0_TMG2_REG [regs EX_CS0_TMG2_REG ]
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set EX_CS0_TMG3_REG [regs EX_CS0_TMG3_REG ]
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set EX_CLOCK_DIV_REG [regs EX_CLOCK_DIV_REG ]
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set EX_MFSM_REG [regs EX_MFSM_REG ]
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set EX_CSFSM_REG [regs EX_CSFSM_REG ]
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set EX_WRFSM_REG [regs EX_WRFSM_REG ]
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set EX_RDFSM_REG [regs EX_RDFSM_REG ]
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echo [format "EX_CSEN_REG (0x%x): 0x%x" $EX_CSEN_REG [mrw $EX_CSEN_REG]]
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echo [format "EX_CS0_SEG_REG (0x%x): 0x%x" $EX_CS0_SEG_REG [mrw $EX_CS0_SEG_REG]]
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echo [format "EX_CS0_CFG_REG (0x%x): 0x%x" $EX_CS0_CFG_REG [mrw $EX_CS0_CFG_REG]]
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echo [format "EX_CS0_TMG1_REG (0x%x): 0x%x" $EX_CS0_TMG1_REG [mrw $EX_CS0_TMG1_REG]]
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echo [format "EX_CS0_TMG2_REG (0x%x): 0x%x" $EX_CS0_TMG2_REG [mrw $EX_CS0_TMG2_REG]]
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echo [format "EX_CS0_TMG3_REG (0x%x): 0x%x" $EX_CS0_TMG3_REG [mrw $EX_CS0_TMG3_REG]]
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echo [format "EX_CLOCK_DIV_REG (0x%x): 0x%x" $EX_CLOCK_DIV_REG [mrw $EX_CLOCK_DIV_REG]]
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echo [format "EX_MFSM_REG (0x%x): 0x%x" $EX_MFSM_REG [mrw $EX_MFSM_REG]]
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echo [format "EX_CSFSM_REG (0x%x): 0x%x" $EX_CSFSM_REG [mrw $EX_CSFSM_REG]]
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echo [format "EX_WRFSM_REG (0x%x): 0x%x" $EX_WRFSM_REG [mrw $EX_WRFSM_REG]]
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echo [format "EX_RDFSM_REG (0x%x): 0x%x" $EX_RDFSM_REG [mrw $EX_RDFSM_REG]]
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}
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proc showGPIO {} {
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echo "This is the current GPIO register setup"
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# GPIO outputs register
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set GPIO_OUTPUT_REG [regs GPIO_OUTPUT_REG]
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# GPIO Output Enable register
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set GPIO_OE_REG [regs GPIO_OE_REG]
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set GPIO_HI_INT_ENABLE_REG [regs GPIO_HI_INT_ENABLE_REG]
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set GPIO_LO_INT_ENABLE_REG [regs GPIO_LO_INT_ENABLE_REG]
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# GPIO input register
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set GPIO_INPUT_REG [regs GPIO_INPUT_REG]
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set APB_ACCESS_WS_REG [regs APB_ACCESS_WS_REG]
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set MUX_CONF_REG [regs MUX_CONF_REG]
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set SYSCONF_REG [regs SYSCONF_REG]
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set GPIO_ARM_ID_REG [regs GPIO_ARM_ID_REG]
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set GPIO_BOOTSTRAP_REG [regs GPIO_BOOTSTRAP_REG]
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set GPIO_LOCK_REG [regs GPIO_LOCK_REG]
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set GPIO_IOCTRL_REG [regs GPIO_IOCTRL_REG]
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set GPIO_DEVID_REG [regs GPIO_DEVID_REG]
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echo [format "GPIO_OUTPUT_REG (0x%x): 0x%x" $GPIO_OUTPUT_REG [mrw $GPIO_OUTPUT_REG]]
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echo [format "GPIO_OE_REG (0x%x): 0x%x" $GPIO_OE_REG [mrw $GPIO_OE_REG]]
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echo [format "GPIO_HI_INT_ENABLE_REG(0x%x): 0x%x" $GPIO_HI_INT_ENABLE_REG [mrw $GPIO_HI_INT_ENABLE_REG]]
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echo [format "GPIO_LO_INT_ENABLE_REG(0x%x): 0x%x" $GPIO_LO_INT_ENABLE_REG [mrw $GPIO_LO_INT_ENABLE_REG]]
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echo [format "GPIO_INPUT_REG (0x%x): 0x%x" $GPIO_INPUT_REG [mrw $GPIO_INPUT_REG]]
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echo [format "APB_ACCESS_WS_REG (0x%x): 0x%x" $APB_ACCESS_WS_REG [mrw $APB_ACCESS_WS_REG]]
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echo [format "MUX_CONF_REG (0x%x): 0x%x" $MUX_CONF_REG [mrw $MUX_CONF_REG]]
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echo [format "SYSCONF_REG (0x%x): 0x%x" $SYSCONF_REG [mrw $SYSCONF_REG]]
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echo [format "GPIO_ARM_ID_REG (0x%x): 0x%x" $GPIO_ARM_ID_REG [mrw $GPIO_ARM_ID_REG]]
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echo [format "GPIO_BOOTSTRAP_REG (0x%x): 0x%x" $GPIO_BOOTSTRAP_REG [mrw $GPIO_BOOTSTRAP_REG]]
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echo [format "GPIO_LOCK_REG (0x%x): 0x%x" $GPIO_LOCK_REG [mrw $GPIO_LOCK_REG]]
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echo [format "GPIO_IOCTRL_REG (0x%x): 0x%x" $GPIO_IOCTRL_REG [mrw $GPIO_IOCTRL_REG]]
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echo [format "GPIO_DEVID_REG (0x%x): 0x%x" $GPIO_DEVID_REG [mrw $GPIO_DEVID_REG]]
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}
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# converted from u-boot/cpu/arm1136/comcerto/bsp100.c (HAL_get_amba_clk())
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proc showAmbaClk {} {
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set CFG_REFCLKFREQ [config CFG_REFCLKFREQ]
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set CLKCORE_AHB_CLK_CNTRL [regs CLKCORE_AHB_CLK_CNTRL]
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set PLL_CLK_BYPASS [regs PLL_CLK_BYPASS]
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echo [format "CLKCORE_AHB_CLK_CNTRL (0x%x): 0x%x" $CLKCORE_AHB_CLK_CNTRL [mrw $CLKCORE_AHB_CLK_CNTRL]]
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set value [read_memory $CLKCORE_AHB_CLK_CNTRL 32 1]
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# see if the PLL is in bypass mode
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set bypass [expr {($value & $PLL_CLK_BYPASS) >> 24}]
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echo [format "PLL bypass bit: %d" $bypass]
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if {$bypass == 1} {
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echo [format "Amba Clk is set to REFCLK: %d (MHz)" [expr {$CFG_REFCLKFREQ/1000000}]]
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} else {
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# nope, extract x,y,w and compute the PLL output freq.
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set x [expr {($value & 0x0001F0000) >> 16}]
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echo [format "x: %d" $x]
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set y [expr {($value & 0x00000007F)}]
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echo [format "y: %d" $y]
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set w [expr {($value & 0x000000300) >> 8}]
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echo [format "w: %d" $w]
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echo [format "Amba PLL Clk: %d (MHz)" [expr {($CFG_REFCLKFREQ * $y / (($w + 1) * ($x + 1) * 2))/1000000}]]
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}
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}
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# converted from u-boot/cpu/arm1136/comcerto/bsp100.c (HAL_set_amba_clk())
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# this clock is useb by all peripherals (DDR2, ethernet, ebus, etc)
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proc setupAmbaClk {} {
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set CLKCORE_PLL_STATUS [regs CLKCORE_PLL_STATUS]
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set CLKCORE_AHB_CLK_CNTRL [regs CLKCORE_AHB_CLK_CNTRL]
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set ARM_PLL_BY_CTRL [regs ARM_PLL_BY_CTRL]
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set ARM_AHB_BYP [regs ARM_AHB_BYP]
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set PLL_DISABLE [regs PLL_DISABLE]
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set PLL_CLK_BYPASS [regs PLL_CLK_BYPASS]
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set AHB_PLL_BY_CTRL [regs AHB_PLL_BY_CTRL]
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set DIV_BYPASS [regs DIV_BYPASS]
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set AHBCLK_PLL_LOCK [regs AHBCLK_PLL_LOCK]
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set CFG_REFCLKFREQ [config CFG_REFCLKFREQ]
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set CONFIG_SYS_HZ_CLOCK [config CONFIG_SYS_HZ_CLOCK]
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set w [config w_amba]
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set x [config x_amba]
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set y [config y_amba]
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echo [format "Setting Amba PLL to lock to %d MHz" [expr {$CONFIG_SYS_HZ_CLOCK/1000000}]]
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#echo [format "setupAmbaClk: w= %d" $w]
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#echo [format "setupAmbaClk: x= %d" $x]
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#echo [format "setupAmbaClk: y= %d" $y]
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# set PLL into BYPASS mode using MUX
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mmw $CLKCORE_AHB_CLK_CNTRL $PLL_CLK_BYPASS 0x0
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# do an internal PLL bypass
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mmw $CLKCORE_AHB_CLK_CNTRL $AHB_PLL_BY_CTRL 0x0
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# wait 500us (ARM running @24Mhz -> 12000 cycles => 500us)
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# openocd smallest resolution is 1ms so, wait 1ms
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sleep 1
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# disable the PLL
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mmw $CLKCORE_AHB_CLK_CNTRL $PLL_DISABLE 0x0
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# wait 1ms
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sleep 1
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# enable the PLL
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mmw $CLKCORE_AHB_CLK_CNTRL 0x0 $PLL_DISABLE
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sleep 1
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# set X, W and X
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mmw $CLKCORE_AHB_CLK_CNTRL 0x0 0xFFFFFF
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mmw $CLKCORE_AHB_CLK_CNTRL [expr {($x << 16) + ($w << 8) + $y}] 0x0
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# wait for PLL to lock
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echo "Waiting for Amba PLL to lock"
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while {[mrw $CLKCORE_PLL_STATUS] & $AHBCLK_PLL_LOCK == 0} { sleep 1 }
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# remove the internal PLL bypass
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mmw $CLKCORE_AHB_CLK_CNTRL 0x0 $AHB_PLL_BY_CTRL
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# remove PLL from BYPASS mode using MUX
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mmw $CLKCORE_AHB_CLK_CNTRL 0x0 $PLL_CLK_BYPASS
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}
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# converted from u-boot/cpu/arm1136/comcerto/bsp100.c (HAL_get_arm_clk())
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proc showArmClk {} {
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set CFG_REFCLKFREQ [config CFG_REFCLKFREQ]
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set CLKCORE_ARM_CLK_CNTRL [regs CLKCORE_ARM_CLK_CNTRL]
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set PLL_CLK_BYPASS [regs PLL_CLK_BYPASS]
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echo [format "CLKCORE_ARM_CLK_CNTRL (0x%x): 0x%x" $CLKCORE_ARM_CLK_CNTRL [mrw $CLKCORE_ARM_CLK_CNTRL]]
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set value [read_memory $CLKCORE_ARM_CLK_CNTRL 32 1]
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# see if the PLL is in bypass mode
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set bypass [expr {($value & $PLL_CLK_BYPASS) >> 24}]
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echo [format "PLL bypass bit: %d" $bypass]
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if {$bypass == 1} {
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echo [format "Amba Clk is set to REFCLK: %d (MHz)" [expr {$CFG_REFCLKFREQ/1000000}]]
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} else {
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# nope, extract x,y,w and compute the PLL output freq.
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set x [expr {($value & 0x0001F0000) >> 16}]
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echo [format "x: %d" $x]
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set y [expr {($value & 0x00000007F)}]
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echo [format "y: %d" $y]
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set w [expr {($value & 0x000000300) >> 8}]
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echo [format "w: %d" $w]
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echo [format "Arm PLL Clk: %d (MHz)" [expr {($CFG_REFCLKFREQ * $y / (($w + 1) * ($x + 1) * 2))/1000000}]]
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}
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}
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# converted from u-boot/cpu/arm1136/comcerto/bsp100.c (HAL_set_arm_clk())
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# Arm Clock is used by two ARM1136 cores
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proc setupArmClk {} {
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set CLKCORE_PLL_STATUS [regs CLKCORE_PLL_STATUS]
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set CLKCORE_ARM_CLK_CNTRL [regs CLKCORE_ARM_CLK_CNTRL]
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set ARM_PLL_BY_CTRL [regs ARM_PLL_BY_CTRL]
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set ARM_AHB_BYP [regs ARM_AHB_BYP]
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set PLL_DISABLE [regs PLL_DISABLE]
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set PLL_CLK_BYPASS [regs PLL_CLK_BYPASS]
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set AHB_PLL_BY_CTRL [regs AHB_PLL_BY_CTRL]
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set DIV_BYPASS [regs DIV_BYPASS]
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set FCLK_PLL_LOCK [regs FCLK_PLL_LOCK]
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set CFG_REFCLKFREQ [config CFG_REFCLKFREQ]
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set CFG_ARM_CLOCK [config CFG_ARM_CLOCK]
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set w [config w_arm]
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set x [config x_arm]
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set y [config y_arm]
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echo [format "Setting Arm PLL to lock to %d MHz" [expr {$CFG_ARM_CLOCK/1000000}]]
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#echo [format "setupArmClk: w= %d" $w]
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#echo [format "setupArmaClk: x= %d" $x]
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#echo [format "setupArmaClk: y= %d" $y]
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# set PLL into BYPASS mode using MUX
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mmw $CLKCORE_ARM_CLK_CNTRL $PLL_CLK_BYPASS 0x0
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# do an internal PLL bypass
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mmw $CLKCORE_ARM_CLK_CNTRL $ARM_PLL_BY_CTRL 0x0
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# wait 500us (ARM running @24Mhz -> 12000 cycles => 500us)
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# openocd smallest resolution is 1ms so, wait 1ms
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sleep 1
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# disable the PLL
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mmw $CLKCORE_ARM_CLK_CNTRL $PLL_DISABLE 0x0
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# wait 1ms
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sleep 1
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# enable the PLL
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mmw $CLKCORE_ARM_CLK_CNTRL 0x0 $PLL_DISABLE
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sleep 1
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# set X, W and X
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mmw $CLKCORE_ARM_CLK_CNTRL 0x0 0xFFFFFF
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mmw $CLKCORE_ARM_CLK_CNTRL [expr {($x << 16) + ($w << 8) + $y}] 0x0
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# wait for PLL to lock
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echo "Waiting for Amba PLL to lock"
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while {[mrw $CLKCORE_PLL_STATUS] & $FCLK_PLL_LOCK == 0} { sleep 1 }
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# remove the internal PLL bypass
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mmw $CLKCORE_ARM_CLK_CNTRL 0x0 $ARM_PLL_BY_CTRL
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# remove PLL from BYPASS mode using MUX
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mmw $CLKCORE_ARM_CLK_CNTRL 0x0 $PLL_CLK_BYPASS
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}
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proc setupPLL {} {
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echo "PLLs setup"
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setupAmbaClk
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setupArmClk
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}
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# converted from u-boot/cpu/arm1136/bsp100.c:SoC_mem_init()
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proc setupDDR2 {} {
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echo "Configuring DDR2"
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set MEMORY_BASE_ADDR [regs MEMORY_BASE_ADDR]
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set MEMORY_MAX_ADDR [regs MEMORY_MAX_ADDR]
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set MEMORY_CR [regs MEMORY_CR]
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set BLOCK_RESET_REG [regs BLOCK_RESET_REG]
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set DDR_RST [regs DDR_RST]
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# put DDR controller in reset (so that it is reset and correctly configured)
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# this is only necessary if DDR was previously confiured
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# and not reset.
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mmw $BLOCK_RESET_REG 0x0 $DDR_RST
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set M [expr {1024 * 1024}]
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set DDR_SZ_1024M [expr {1024 * $M}]
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set DDR_SZ_256M [expr {256 * $M}]
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set DDR_SZ_128M [expr {128 * $M}]
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set DDR_SZ_64M [expr {64 * $M}]
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# ooma_board_detect returns DDR2 memory size
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set tmp [ooma_board_detect]
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if {$tmp == "128M"} {
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echo "DDR2 size 128MB"
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set ddr_size $DDR_SZ_128M
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} elseif {$tmp == "256M"} {
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echo "DDR2 size 256MB"
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set ddr_size $DDR_SZ_256M
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} else {
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echo "Don't know how to handle this DDR2 size?"
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}
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# Memory setup register
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mww $MEMORY_MAX_ADDR [expr {($ddr_size - 1) + $MEMORY_BASE_ADDR}]
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# disable ROM remap
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mww $MEMORY_CR 0x0
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# Take DDR controller out of reset
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mmw $BLOCK_RESET_REG $DDR_RST 0x0
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# min. 20 ops delay
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sleep 1
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# This will setup Denali DDR2 controller
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if {$tmp == "128M"} {
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configureDDR2regs_128M
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} elseif {$tmp == "256M"} {
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configureDDR2regs_256M
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} else {
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echo "Don't know how to configure DDR2 setup?"
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}
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}
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proc showDDR2 {} {
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set DENALI_CTL_00_DATA [regs DENALI_CTL_00_DATA]
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set DENALI_CTL_01_DATA [regs DENALI_CTL_01_DATA]
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set DENALI_CTL_02_DATA [regs DENALI_CTL_02_DATA]
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set DENALI_CTL_03_DATA [regs DENALI_CTL_03_DATA]
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set DENALI_CTL_04_DATA [regs DENALI_CTL_04_DATA]
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set DENALI_CTL_05_DATA [regs DENALI_CTL_05_DATA]
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set DENALI_CTL_06_DATA [regs DENALI_CTL_06_DATA]
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set DENALI_CTL_07_DATA [regs DENALI_CTL_07_DATA]
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set DENALI_CTL_08_DATA [regs DENALI_CTL_08_DATA]
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set DENALI_CTL_09_DATA [regs DENALI_CTL_09_DATA]
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set DENALI_CTL_10_DATA [regs DENALI_CTL_10_DATA]
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set DENALI_CTL_11_DATA [regs DENALI_CTL_11_DATA]
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set DENALI_CTL_12_DATA [regs DENALI_CTL_12_DATA]
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set DENALI_CTL_13_DATA [regs DENALI_CTL_13_DATA]
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set DENALI_CTL_14_DATA [regs DENALI_CTL_14_DATA]
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set DENALI_CTL_15_DATA [regs DENALI_CTL_15_DATA]
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set DENALI_CTL_16_DATA [regs DENALI_CTL_16_DATA]
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set DENALI_CTL_17_DATA [regs DENALI_CTL_17_DATA]
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set DENALI_CTL_18_DATA [regs DENALI_CTL_18_DATA]
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set DENALI_CTL_19_DATA [regs DENALI_CTL_19_DATA]
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set DENALI_CTL_20_DATA [regs DENALI_CTL_20_DATA]
|
|
|
|
set tmp [mr64bit $DENALI_CTL_00_DATA]
|
|
echo [format "DENALI_CTL_00_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_00_DATA $tmp(1) $tmp(0)]
|
|
set tmp [mr64bit $DENALI_CTL_01_DATA]
|
|
echo [format "DENALI_CTL_01_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_01_DATA $tmp(1) $tmp(0)]
|
|
set tmp [mr64bit $DENALI_CTL_02_DATA]
|
|
echo [format "DENALI_CTL_02_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_02_DATA $tmp(1) $tmp(0)]
|
|
set tmp [mr64bit $DENALI_CTL_03_DATA]
|
|
echo [format "DENALI_CTL_03_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_03_DATA $tmp(1) $tmp(0)]
|
|
set tmp [mr64bit $DENALI_CTL_04_DATA]
|
|
echo [format "DENALI_CTL_04_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_04_DATA $tmp(1) $tmp(0)]
|
|
set tmp [mr64bit $DENALI_CTL_05_DATA]
|
|
echo [format "DENALI_CTL_05_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_05_DATA $tmp(1) $tmp(0)]
|
|
set tmp [mr64bit $DENALI_CTL_06_DATA]
|
|
echo [format "DENALI_CTL_06_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_06_DATA $tmp(1) $tmp(0)]
|
|
set tmp [mr64bit $DENALI_CTL_07_DATA]
|
|
echo [format "DENALI_CTL_07_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_07_DATA $tmp(1) $tmp(0)]
|
|
set tmp [mr64bit $DENALI_CTL_08_DATA]
|
|
echo [format "DENALI_CTL_08_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_08_DATA $tmp(1) $tmp(0)]
|
|
set tmp [mr64bit $DENALI_CTL_09_DATA]
|
|
echo [format "DENALI_CTL_09_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_09_DATA $tmp(1) $tmp(0)]
|
|
set tmp [mr64bit $DENALI_CTL_10_DATA]
|
|
echo [format "DENALI_CTL_10_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_10_DATA $tmp(1) $tmp(0)]
|
|
set tmp [mr64bit $DENALI_CTL_11_DATA]
|
|
echo [format "DENALI_CTL_11_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_11_DATA $tmp(1) $tmp(0)]
|
|
set tmp [mr64bit $DENALI_CTL_12_DATA]
|
|
echo [format "DENALI_CTL_12_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_12_DATA $tmp(1) $tmp(0)]
|
|
set tmp [mr64bit $DENALI_CTL_13_DATA]
|
|
echo [format "DENALI_CTL_13_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_13_DATA $tmp(1) $tmp(0)]
|
|
set tmp [mr64bit $DENALI_CTL_14_DATA]
|
|
echo [format "DENALI_CTL_14_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_14_DATA $tmp(1) $tmp(0)]
|
|
set tmp [mr64bit $DENALI_CTL_15_DATA]
|
|
echo [format "DENALI_CTL_15_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_15_DATA $tmp(1) $tmp(0)]
|
|
set tmp [mr64bit $DENALI_CTL_16_DATA]
|
|
echo [format "DENALI_CTL_16_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_16_DATA $tmp(1) $tmp(0)]
|
|
set tmp [mr64bit $DENALI_CTL_17_DATA]
|
|
echo [format "DENALI_CTL_17_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_17_DATA $tmp(1) $tmp(0)]
|
|
set tmp [mr64bit $DENALI_CTL_18_DATA]
|
|
echo [format "DENALI_CTL_18_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_18_DATA $tmp(1) $tmp(0)]
|
|
set tmp [mr64bit $DENALI_CTL_19_DATA]
|
|
echo [format "DENALI_CTL_19_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_19_DATA $tmp(1) $tmp(0)]
|
|
set tmp [mr64bit $DENALI_CTL_20_DATA]
|
|
echo [format "DENALI_CTL_20_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_20_DATA $tmp(1) $tmp(0)]
|
|
|
|
}
|
|
|
|
proc initC100 {} {
|
|
# this follows u-boot/cpu/arm1136/start.S
|
|
set GPIO_LOCK_REG [regs GPIO_LOCK_REG]
|
|
set GPIO_IOCTRL_REG [regs GPIO_IOCTRL_REG]
|
|
set GPIO_IOCTRL_VAL [regs GPIO_IOCTRL_VAL]
|
|
set APB_ACCESS_WS_REG [regs APB_ACCESS_WS_REG]
|
|
set ASA_ARAM_BASEADDR [regs ASA_ARAM_BASEADDR]
|
|
set ASA_ARAM_TC_CR_REG [regs ASA_ARAM_TC_CR_REG]
|
|
set ASA_EBUS_BASEADDR [regs ASA_EBUS_BASEADDR]
|
|
set ASA_EBUS_TC_CR_REG [regs ASA_EBUS_TC_CR_REG]
|
|
set ASA_TC_REQIDMAEN [regs ASA_TC_REQIDMAEN]
|
|
set ASA_TC_REQTDMEN [regs ASA_TC_REQTDMEN]
|
|
set ASA_TC_REQIPSECUSBEN [regs ASA_TC_REQIPSECUSBEN]
|
|
set ASA_TC_REQARM0EN [regs ASA_TC_REQARM0EN]
|
|
set ASA_TC_REQARM1EN [regs ASA_TC_REQARM1EN]
|
|
set ASA_TC_REQMDMAEN [regs ASA_TC_REQMDMAEN]
|
|
set INTC_ARM1_CONTROL_REG [regs INTC_ARM1_CONTROL_REG]
|
|
|
|
|
|
# unlock writing to IOCTRL register
|
|
mww $GPIO_LOCK_REG $GPIO_IOCTRL_VAL
|
|
# enable address lines A15-A21
|
|
mmw $GPIO_IOCTRL_REG 0xf 0x0
|
|
# set ARM into supervisor mode (SVC32)
|
|
# disable IRQ, FIQ
|
|
# Do I need this in JTAG mode?
|
|
# it really should be done as 'and ~0x1f | 0xd3 but
|
|
# openocd does not support this yet
|
|
reg cpsr 0xd3
|
|
# /*
|
|
# * flush v4 I/D caches
|
|
# */
|
|
# mov r0, #0
|
|
# mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
|
|
arm mcr 15 0 7 7 0 0x0
|
|
# mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
|
|
arm mcr 15 0 8 7 0 0x0
|
|
|
|
# /*
|
|
# * disable MMU stuff and caches
|
|
# */
|
|
# mrc p15, 0, r0, c1, c0, 0
|
|
arm mrc 15 0 1 0 0
|
|
# bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
|
|
# bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
|
|
# orr r0, r0, #0x00000002 @ set bit 2 (A) Align
|
|
# orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
|
|
# orr r0, r0, #0x00400000 @ set bit 22 (U)
|
|
# mcr p15, 0, r0, c1, c0, 0
|
|
arm mcr 15 0 1 0 0 0x401002
|
|
# This is from bsp_init() in u-boot/boards/mindspeed/ooma-darwin/board.c
|
|
# APB init
|
|
# // Setting APB Bus Wait states to 1, set post write
|
|
# (*(volatile u32*)(APB_ACCESS_WS_REG)) = 0x40;
|
|
mww $APB_ACCESS_WS_REG 0x40
|
|
# AHB init
|
|
# // enable all 6 masters for ARAM
|
|
mmw $ASA_ARAM_TC_CR_REG [expr {$ASA_TC_REQIDMAEN | $ASA_TC_REQTDMEN | $ASA_TC_REQIPSECUSBEN | $ASA_TC_REQARM0EN | $ASA_TC_REQARM1EN | $ASA_TC_REQMDMAEN}] 0x0
|
|
# // enable all 6 masters for EBUS
|
|
mmw $ASA_EBUS_TC_CR_REG [expr {$ASA_TC_REQIDMAEN | $ASA_TC_REQTDMEN | $ASA_TC_REQIPSECUSBEN | $ASA_TC_REQARM0EN | $ASA_TC_REQARM1EN | $ASA_TC_REQMDMAEN}] 0x0
|
|
|
|
# ARAM init
|
|
# // disable pipeline mode in ARAM
|
|
# I don't think this is documented anywhere?
|
|
mww $INTC_ARM1_CONTROL_REG 0x1
|
|
# configure clocks
|
|
setupPLL
|
|
# setupUART0 must be run before setupDDR2 as setupDDR2 uses UART.
|
|
setupUART0
|
|
# enable cache
|
|
# ? (u-boot does nothing here)
|
|
# DDR2 memory init
|
|
setupDDR2
|
|
putsUART0 "C100 initialization complete.\n"
|
|
echo "C100 initialization complete."
|
|
}
|
|
|
|
# show current state of watchdog timer
|
|
proc showWatchdog {} {
|
|
set TIMER_WDT_HIGH_BOUND [regs TIMER_WDT_HIGH_BOUND]
|
|
set TIMER_WDT_CONTROL [regs TIMER_WDT_CONTROL]
|
|
set TIMER_WDT_CURRENT_COUNT [regs TIMER_WDT_CURRENT_COUNT]
|
|
|
|
echo [format "TIMER_WDT_HIGH_BOUND (0x%x): 0x%x" $TIMER_WDT_HIGH_BOUND [mrw $TIMER_WDT_HIGH_BOUND]]
|
|
echo [format "TIMER_WDT_CONTROL (0x%x): 0x%x" $TIMER_WDT_CONTROL [mrw $TIMER_WDT_CONTROL]]
|
|
echo [format "TIMER_WDT_CURRENT_COUNT (0x%x): 0x%x" $TIMER_WDT_CURRENT_COUNT [mrw $TIMER_WDT_CURRENT_COUNT]]
|
|
}
|
|
|
|
# converted from u-boot/cpu/arm1136/comcerto/intrrupts.c:void reset_cpu (ulong ignored)
|
|
# this will trigger watchdog reset
|
|
# the sw. reset does not work on C100
|
|
# watchdog reset effectively works as hw. reset
|
|
proc reboot {} {
|
|
set TIMER_WDT_HIGH_BOUND [regs TIMER_WDT_HIGH_BOUND]
|
|
set TIMER_WDT_CONTROL [regs TIMER_WDT_CONTROL]
|
|
set TIMER_WDT_CURRENT_COUNT [regs TIMER_WDT_CURRENT_COUNT]
|
|
|
|
# allow the counter to count to high value before triggering
|
|
# this is because register writes are slow over JTAG and
|
|
# I don't want to miss the high_bound==curr_count condition
|
|
mww $TIMER_WDT_HIGH_BOUND 0xffffff
|
|
mww $TIMER_WDT_CURRENT_COUNT 0x0
|
|
echo "JTAG speed lowered to 100kHz"
|
|
adapter speed 100
|
|
mww $TIMER_WDT_CONTROL 0x1
|
|
# wait until the reset
|
|
echo -n "Waiting for watchdog to trigger..."
|
|
#while {[mrw $TIMER_WDT_CONTROL] == 1} {
|
|
# echo [format "TIMER_WDT_CURRENT_COUNT (0x%x): 0x%x" $TIMER_WDT_CURRENT_COUNT [mrw $TIMER_WDT_CURRENT_COUNT]]
|
|
# sleep 1
|
|
#
|
|
#}
|
|
while {[c100.cpu curstate] != "running"} { sleep 1}
|
|
echo "done."
|
|
echo [format "Note that C100 is in %s state, type halt to stop" [c100.cpu curstate]]
|
|
}
|