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c986b4dbf2
BL602, BL702 and BL702L series of chips are sharing same architecture, so they all need same software reset mechanism as well. Only difference (in terms of configuration needed for JTAG) are TAP ID, workarea address and size. This is addressed by creating bl602_common.cfg tcl file, which contains all those common stuff between the chips. The script is prefixed by bl602, as this was first *publicly* available chip from Bouffalo with this architecture. This patch also improves reset mechanism. Previous reset mechanism did not worked properly when slower JTAG adapter was used (it attached too late). New reset mechanism uses various methods to keep CPU in BootROM, until the JTAG adapter does not attach again after reset. Additionally, we trigger SW Reset by directly using DMI commands to write to register with system bus method, to avoid getting error about unsuccessful write. The new method works on both FT232H (8MHz JTAG clock) and unnamed CMSIS-DAP dongle (1.5MHz JTAG clock). Change-Id: I5be3694927793fd3f64c9ed4ee6ded2db0d25cae Signed-off-by: Marek Kraus <gamelaster@outlook.com> Reviewed-on: https://review.openocd.org/c/openocd/+/8593 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
48 lines
1.1 KiB
INI
48 lines
1.1 KiB
INI
# SPDX-License-Identifier: GPL-2.0-or-later
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#
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# Bouffalo Labs BL702L and BL704L target
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#
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# https://en.bouffalolab.com/product/?type=detail&id=26
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#
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# Default JTAG pins: (if not changed by eFuse configuration)
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# TMS - GPIO0
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# TDI - GPIO1
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# TCK - GPIO2
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# TDO - GPIO7
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#
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if { [info exists CHIPNAME] } {
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set BL602_CHIPNAME $CHIPNAME
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} else {
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set BL602_CHIPNAME bl702l
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}
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set CPUTAPID 0x20000e05
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# For work-area we use beginning of OCRAM, since BL702L have only ITCM, which can be taken
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# by L1 cache and XIP during runtime.
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set WORKAREAADDR 0x42020000
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set WORKAREASIZE 0x10000
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source [find target/bl602_common.cfg]
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# JTAG reset is broken. Read comment of bl602_sw_reset function for more information
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# On BL702L, we are forcing boot into ISP mode, so chip stays in BootROM until JTAG re-attach
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$_TARGETNAME configure -event reset-assert {
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halt
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# Restore clocks to defaults
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bl602_restore_clock_defaults
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# In HBN_RSV2, set HBN_RELEASE_CORE to HBN_RELEASE_CORE_FLAG (4)
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# and HBN_USER_BOOT_SEL to 1 (ISP)
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mww 0x4000f108 0x44000000
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# Perform software reset
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bl602_sw_reset
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# Reset HBN_RSV2 so BootROM will not force ISP mode again
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mww 0x4000f108 0x00000000
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}
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