mirror of
https://git.code.sf.net/p/openocd/code
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e6505b0489
For historical reasons, no license information was added to the
tcl files. This makes trivial adding the SPDX tag through script:
fgrep -rL SPDX tcl/ target| while read a;do \
sed -i '1{i# SPDX-License-Identifier: GPL-2.0-or-later\n
}' $a;done
With no specific license information from the author, let's extend
the OpenOCD project license GPL-2.0-or-later to the files.
Change-Id: I7b2610300b24cccd07bfa6fb5f1266970d5d3a1b
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7027
Tested-by: jenkins
92 lines
3.2 KiB
INI
92 lines
3.2 KiB
INI
# SPDX-License-Identifier: GPL-2.0-or-later
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######################################
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# Target: Atmel AT91SAM9260
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######################################
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source [find target/at91sam9261.cfg]
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reset_config trst_and_srst
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adapter speed 4
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adapter srst delay 200
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jtag_ntrst_delay 200
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scan_chain
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$_TARGETNAME configure -event reset-start {
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# at reset chip runs at 32khz
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adapter speed 8
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}
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$_TARGETNAME configure -event reset-init {at91sam_init}
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# Flash configuration
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#flash bank <name> cfi <base> <size> <chip width> <bus width> <target>
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set _FLASHNAME $_CHIPNAME.flash
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flash bank $_FLASHNAME cfi 0x10000000 0x01000000 2 2 $_TARGETNAME
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# Faster memory downloads. This is disabled automatically during
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# reset init since all reset init sequences are too short for
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# fast memory access
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arm7_9 dcc_downloads enable
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arm7_9 fast_memory_access enable
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proc at91sam_init { } {
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mww 0xfffffd08 0xa5000501 ;# RSTC_MR : enable user reset
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mww 0xfffffd44 0x00008000 ;# WDT_MR : disable watchdog
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mww 0xfffffc20 0x00004001 ;# CKGR_MOR : enable the main oscillator
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sleep 20 ;# wait 20 ms
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mww 0xfffffc30 0x00000001 ;# PMC_MCKR : switch to main oscillator
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sleep 10 ;# wait 10 ms
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mww 0xfffffc28 0x2060bf09 ;# CKGR_PLLAR: Set PLLA Register for 198,656MHz
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sleep 20 ;# wait 20 ms
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mww 0xfffffc30 0x00000101 ;# PMC_MCKR : Select prescaler
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sleep 10 ;# wait 10 ms
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mww 0xfffffc30 0x00000102 ;# PMC_MCKR : Clock from PLLA is selected
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sleep 10 ;# wait 10 ms
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# Now run at anything fast... ie: 10mhz!
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adapter speed 10000 ;# Increase JTAG Speed to 6 MHz
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mww 0xffffec00 0x0a0a0a0a ;# SMC_SETUP0 : Setup SMC for Intel NOR Flash JS28F128P30T85 128MBit
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mww 0xffffec04 0x0b0b0b0b ;# SMC_PULSE0
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mww 0xffffec08 0x00160016 ;# SMC_CYCLE0
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mww 0xffffec0c 0x00161003 ;# SMC_MODE0
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mww 0xfffff870 0xffff0000 ;# PIO_ASR : Select peripheral function for D15..D31
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mww 0xfffff804 0xffff0000 ;# PIO_PDR : Disable PIO function for D15..D31
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mww 0xffffef1c 0x2 ;# EBI_CSA : Assign EBI Chip Select 1 to SDRAM
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mww 0xffffea08 0x85227259 ;# SDRAMC_CR : Configure SDRAM (2 x Samsung K4S561632H-UC75 : 4M x 16Bit x 4 Banks)
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#mww 0xffffea08 0x85227254 ;# SDRAMC_CR : Configure SDRAM (2 x Samsung K4S641632H-UC75 : 1M x 16Bit x 4 Banks)
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mww 0xffffea00 0x1 ;# SDRAMC_MR : issue a NOP command
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mww 0x20000000 0
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mww 0xffffea00 0x2 ;# SDRAMC_MR : issue an 'All Banks Precharge' command
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mww 0x20000000 0
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mww 0xffffea00 0x4 ;# SDRAMC_MR : issue 8 x 'Auto-Refresh' Command
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mww 0x20000000 0
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mww 0xffffea00 0x4
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mww 0x20000000 0
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mww 0xffffea00 0x4
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mww 0x20000000 0
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mww 0xffffea00 0x4
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mww 0x20000000 0
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mww 0xffffea00 0x4
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mww 0x20000000 0
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mww 0xffffea00 0x4
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mww 0x20000000 0
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mww 0xffffea00 0x4
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mww 0x20000000 0
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mww 0xffffea00 0x4
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mww 0x20000000 0
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mww 0xffffea00 0x3 ;# SDRAMC_MR : issue a 'Load Mode Register' command
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mww 0x20000000 0
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mww 0xffffea00 0x0 ;# SDRAMC_MR : normal mode
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mww 0x20000000 0
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mww 0xffffea04 0x5d2 ;# SDRAMC_TR : Set refresh timer count to 15us
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}
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