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https://git.code.sf.net/p/openocd/code
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37f638bb4c
Tested with AT32F415CBT7 and AT32F421C8T7. Change-Id: I453d34b130b6792100db5e7cc33d68a7e0edfb5c Signed-off-by: Marc Schink <dev@zapb.de> Reviewed-on: https://review.openocd.org/c/openocd/+/8668 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
51 lines
1.2 KiB
INI
51 lines
1.2 KiB
INI
# SPDX-License-Identifier: GPL-2.0-or-later
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#
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# Configuration file for Artery AT32F4x family.
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#
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# https://www.arterychip.com/en/product/
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#
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# AT32F4x devices support JTAG and SWD transport.
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source [find target/swj-dp.tcl]
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME at32f4x
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}
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# Work-area is a space in RAM used for flash programming, by default use 4 KiB.
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if { [info exists WORKAREASIZE] } {
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set _WORKAREASIZE $WORKAREASIZE
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} else {
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set _WORKAREASIZE 0x1000
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}
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if { [info exists CPUTAPID] } {
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set _CPUTAPID $CPUTAPID
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} else {
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if { [using_jtag] } {
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set _CPUTAPID 0x4ba00477
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} {
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set _CPUTAPID 0x1ba01477
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}
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}
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swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
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dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
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set _TARGETNAME $_CHIPNAME.cpu
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target create $_TARGETNAME cortex_m -endian little -dap $_CHIPNAME.dap
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$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE
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set _FLASHNAME $_CHIPNAME.flash
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flash bank $_FLASHNAME artery 0x08000000 0 0 0 $_TARGETNAME
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adapter speed 1000
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if {![using_hla]} {
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cortex_m reset_config sysresetreq
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}
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