mirror of
https://git.code.sf.net/p/openocd/code
synced 2024-11-25 23:56:23 +00:00
573a39b36c
For historical reasons, no license information was added to the
tcl files. This makes trivial adding the SPDX tag through script:
fgrep -rL SPDX tcl | while read a;do \
sed -i '1{i# SPDX-License-Identifier: GPL-2.0-or-later\n
}' $a;done
With no specific license information from the author, let's extend
the OpenOCD project license GPL-2.0-or-later to the files.
Change-Id: Ief3da306a6e1978de7dfb8f552f9ff23151f9944
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7030
Tested-by: jenkins
292 lines
7.2 KiB
Tcl
292 lines
7.2 KiB
Tcl
# SPDX-License-Identifier: GPL-2.0-or-later
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set RCC_CR [expr {$RCC_BASE + 0x00}]
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set RCC_CFGR [expr {$RCC_BASE + 0x04}]
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set RCC_CIR [expr {$RCC_BASE + 0x08}]
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set RCC_APB2RSTR [expr {$RCC_BASE + 0x0c}]
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set RCC_APB1RSTR [expr {$RCC_BASE + 0x10}]
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set RCC_AHBENR [expr {$RCC_BASE + 0x14}]
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set RCC_APB2ENR [expr {$RCC_BASE + 0x18}]
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set RCC_APB1ENR [expr {$RCC_BASE + 0x1c}]
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set RCC_BDCR [expr {$RCC_BASE + 0x20}]
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set RCC_CSR [expr {$RCC_BASE + 0x24}]
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proc show_RCC_CR { } {
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if [ catch { set val [show_mmr32_reg RCC_CR] } msg ] {
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error $msg
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}
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show_mmr_bitfield 0 0 $val HSI { OFF ON }
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show_mmr_bitfield 1 1 $val HSIRDY { NOTRDY RDY }
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show_mmr_bitfield 7 3 $val HSITRIM { _NUMBER_ }
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show_mmr_bitfield 15 8 $val HSICAL { _NUMBER_ }
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show_mmr_bitfield 16 16 $val HSEON { OFF ON }
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show_mmr_bitfield 17 17 $val HSERDY { NOTRDY RDY }
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show_mmr_bitfield 18 18 $val HSEBYP { NOTBYPASSED BYPASSED }
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show_mmr_bitfield 19 19 $val CSSON { OFF ON }
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show_mmr_bitfield 24 24 $val PLLON { OFF ON }
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show_mmr_bitfield 25 25 $val PLLRDY { NOTRDY RDY }
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}
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proc show_RCC_CFGR { } {
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if [ catch { set val [show_mmr32_reg RCC_CFGR] } msg ] {
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error $msg
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}
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show_mmr_bitfield 1 0 $val SW { HSI HSE PLL ILLEGAL }
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show_mmr_bitfield 3 2 $val SWS { HSI HSE PLL ILLEGAL }
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show_mmr_bitfield 7 4 $val HPRE { sysclk_div_1 sysclk_div_1 sysclk_div_1 sysclk_div_1 sysclk_div_1 sysclk_div_1 sysclk_div_1 sysclk_div_1 sysclk_div_2 sysclk_div_4 sysclk_div_8 sysclk_div_16 sysclk_div_64 sysclk_div_128 sysclk_div_256 sysclk_div_512 }
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show_mmr_bitfield 10 8 $val PPRE1 { hclk_div1 hclk_div1 hclk_div1 hclk_div1 hclk_div2 hclk_div4 hclk_div8 hclk_div16 }
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show_mmr_bitfield 13 11 $val PPRE2 { hclk_div1 hclk_div1 hclk_div1 hclk_div1 hclk_div2 hclk_div4 hclk_div8 hclk_div16 }
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show_mmr_bitfield 15 14 $val ADCPRE { pclk2_div1 pclk2_div1 pclk2_div1 pclk2_div1 pclk2_div2 pclk2_div4 pclk2_div8 pclk2_div16 }
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show_mmr_bitfield 16 16 $val PLLSRC { HSI_div_2 HSE }
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show_mmr_bitfield 17 17 $val PLLXTPRE { hse_div1 hse_div2 }
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show_mmr_bitfield 21 18 $val PLLMUL { x2 x3 x4 x5 x6 x7 x8 x9 x10 x11 x12 x13 x14 x15 x16 x16 }
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show_mmr_bitfield 22 22 $val USBPRE { div1 div1_5 }
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show_mmr_bitfield 26 24 $val MCO { none none none none SysClk HSI HSE PLL_div2 }
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}
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proc show_RCC_CIR { } {
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if [ catch { set val [show_mmr32_reg RCC_CIR] } msg ] {
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error $msg
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}
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}
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proc show_RCC_APB2RSTR { } {
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if [ catch { set val [ show_mmr32_reg RCC_APB2RSTR] } msg ] {
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error $msg
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}
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for { set x 0 } { $x < 32 } { incr x } {
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set bits($x) xxx
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}
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set bits(15) adc3
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set bits(14) usart1
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set bits(13) tim8
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set bits(12) spi1
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set bits(11) tim1
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set bits(10) adc2
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set bits(9) adc1
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set bits(8) iopg
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set bits(7) iopf
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set bits(6) iope
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set bits(5) iopd
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set bits(4) iopc
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set bits(3) iopb
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set bits(2) iopa
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set bits(1) xxx
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set bits(0) afio
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show_mmr32_bits bits $val
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}
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proc show_RCC_APB1RSTR { } {
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if [ catch { set val [ show_mmr32_reg RCC_APB1RSTR] } msg ] {
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error $msg
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}
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set bits(31) xxx
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set bits(30) xxx
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set bits(29) dac
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set bits(28) pwr
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set bits(27) bkp
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set bits(26) xxx
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set bits(25) can
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set bits(24) xxx
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set bits(23) usb
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set bits(22) i2c2
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set bits(21) i2c1
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set bits(20) uart5
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set bits(19) uart4
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set bits(18) uart3
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set bits(17) uart2
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set bits(16) xxx
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set bits(15) spi3
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set bits(14) spi2
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set bits(13) xxx
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set bits(12) xxx
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set bits(11) wwdg
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set bits(10) xxx
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set bits(9) xxx
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set bits(8) xxx
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set bits(7) xxx
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set bits(6) xxx
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set bits(5) tim7
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set bits(4) tim6
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set bits(3) tim5
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set bits(2) tim4
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set bits(1) tim3
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set bits(0) tim2
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show_mmr32_bits bits $val
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}
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proc show_RCC_AHBENR { } {
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if [ catch { set val [ show_mmr32_reg RCC_AHBENR ] } msg ] {
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error $msg
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}
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set bits(31) xxx
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set bits(30) xxx
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set bits(29) xxx
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set bits(28) xxx
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set bits(27) xxx
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set bits(26) xxx
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set bits(25) xxx
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set bits(24) xxx
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set bits(23) xxx
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set bits(22) xxx
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set bits(21) xxx
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set bits(20) xxx
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set bits(19) xxx
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set bits(18) xxx
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set bits(17) xxx
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set bits(16) xxx
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set bits(15) xxx
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set bits(14) xxx
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set bits(13) xxx
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set bits(12) xxx
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set bits(11) xxx
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set bits(10) sdio
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set bits(9) xxx
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set bits(8) fsmc
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set bits(7) xxx
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set bits(6) crce
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set bits(5) xxx
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set bits(4) flitf
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set bits(3) xxx
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set bits(2) sram
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set bits(1) dma2
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set bits(0) dma1
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show_mmr32_bits bits $val
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}
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proc show_RCC_APB2ENR { } {
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if [ catch { set val [ show_mmr32_reg RCC_APB2ENR ] } msg ] {
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error $msg
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}
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set bits(31) xxx
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set bits(30) xxx
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set bits(29) xxx
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set bits(28) xxx
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set bits(27) xxx
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set bits(26) xxx
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set bits(25) xxx
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set bits(24) xxx
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set bits(23) xxx
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set bits(22) xxx
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set bits(21) xxx
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set bits(20) xxx
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set bits(19) xxx
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set bits(18) xxx
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set bits(17) xxx
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set bits(16) xxx
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set bits(15) adc3
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set bits(14) usart1
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set bits(13) tim8
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set bits(12) spi1
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set bits(11) tim1
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set bits(10) adc2
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set bits(9) adc1
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set bits(8) iopg
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set bits(7) iopf
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set bits(6) iope
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set bits(5) iopd
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set bits(4) iopc
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set bits(3) iopb
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set bits(2) iopa
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set bits(1) xxx
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set bits(0) afio
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show_mmr32_bits bits $val
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}
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proc show_RCC_APB1ENR { } {
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if [ catch { set val [ show_mmr32_reg RCC_APB1ENR ] } msg ] {
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error $msg
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}
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set bits(31) xxx
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set bits(30) xxx
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set bits(29) dac
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set bits(28) pwr
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set bits(27) bkp
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set bits(26) xxx
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set bits(25) can
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set bits(24) xxx
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set bits(23) usb
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set bits(22) i2c2
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set bits(21) i2c1
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set bits(20) usart5
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set bits(19) usart4
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set bits(18) usart3
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set bits(17) usart2
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set bits(16) xxx
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set bits(15) spi3
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set bits(14) spi2
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set bits(13) xxx
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set bits(12) xxx
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set bits(11) wwdg
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set bits(10) xxx
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set bits(9) xxx
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set bits(8) xxx
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set bits(7) xxx
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set bits(6) xxx
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set bits(5) tim7
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set bits(4) tim6
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set bits(3) tim5
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set bits(2) tim4
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set bits(1) tim3
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set bits(0) tim2
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show_mmr32_bits bits $val
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}
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proc show_RCC_BDCR { } {
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if [ catch { set val [ show_mmr32_reg RCC_BDCR ] } msg ] {
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error $msg
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}
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for { set x 0 } { $x < 32 } { incr x } {
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set bits($x) xxx
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}
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set bits(0) lseon
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set bits(1) lserdy
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set bits(2) lsebyp
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set bits(8) rtcsel0
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set bits(9) rtcsel1
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set bits(15) rtcen
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set bits(16) bdrst
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show_mmr32_bits bits $val
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}
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proc show_RCC_CSR { } {
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if [ catch { set val [ show_mmr32_reg RCC_CSR ] } msg ] {
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error $msg
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}
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for { set x 0 } { $x < 32 } { incr x } {
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set bits($x) xxx
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}
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set bits(0) lsion
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set bits(1) lsirdy
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set bits(24) rmvf
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set bits(26) pin
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set bits(27) por
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set bits(28) sft
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set bits(29) iwdg
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set bits(30) wwdg
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set bits(31) lpwr
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show_mmr32_bits bits $val
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}
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proc show_RCC { } {
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show_RCC_CR
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show_RCC_CFGR
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show_RCC_CIR
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show_RCC_APB2RSTR
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show_RCC_APB1RSTR
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show_RCC_AHBENR
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show_RCC_APB2ENR
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show_RCC_APB1ENR
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show_RCC_BDCR
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show_RCC_CSR
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}
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