mirror of
https://git.code.sf.net/p/openocd/code
synced 2024-11-22 09:36:27 +00:00
573a39b36c
For historical reasons, no license information was added to the
tcl files. This makes trivial adding the SPDX tag through script:
fgrep -rL SPDX tcl | while read a;do \
sed -i '1{i# SPDX-License-Identifier: GPL-2.0-or-later\n
}' $a;done
With no specific license information from the author, let's extend
the OpenOCD project license GPL-2.0-or-later to the files.
Change-Id: Ief3da306a6e1978de7dfb8f552f9ff23151f9944
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7030
Tested-by: jenkins
68 lines
3.3 KiB
INI
68 lines
3.3 KiB
INI
# SPDX-License-Identifier: GPL-2.0-or-later
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# SDRAM Controller (SDRAMC) registers
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set AT91_SDRAMC_MR [expr {$AT91_SDRAMC + 0x00}] ;# SDRAM Controller Mode Register
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set AT91_SDRAMC_MODE [expr {0xf << 0}] ;# Command Mode
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set AT91_SDRAMC_MODE_NORMAL 0
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set AT91_SDRAMC_MODE_NOP 1
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set AT91_SDRAMC_MODE_PRECHARGE 2
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set AT91_SDRAMC_MODE_LMR 3
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set AT91_SDRAMC_MODE_REFRESH 4
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set AT91_SDRAMC_MODE_EXT_LMR 5
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set AT91_SDRAMC_MODE_DEEP 6
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set AT91_SDRAMC_TR [expr {$AT91_SDRAMC + 0x04}] ;# SDRAM Controller Refresh Timer Register
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set AT91_SDRAMC_COUNT [expr {0xfff << 0}] ;# Refresh Timer Counter
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set AT91_SDRAMC_CR [expr {$AT91_SDRAMC + 0x08}] ;# SDRAM Controller Configuration Register
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set AT91_SDRAMC_NC [expr {3 << 0}] ;# Number of Column Bits
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set AT91_SDRAMC_NC_8 [expr {0 << 0}]
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set AT91_SDRAMC_NC_9 [expr {1 << 0}]
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set AT91_SDRAMC_NC_10 [expr {2 << 0}]
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set AT91_SDRAMC_NC_11 [expr {3 << 0}]
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set AT91_SDRAMC_NR [expr {3 << 2}] ;# Number of Row Bits
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set AT91_SDRAMC_NR_11 [expr {0 << 2}]
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set AT91_SDRAMC_NR_12 [expr {1 << 2}]
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set AT91_SDRAMC_NR_13 [expr {2 << 2}]
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set AT91_SDRAMC_NB [expr {1 << 4}] ;# Number of Banks
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set AT91_SDRAMC_NB_2 [expr {0 << 4}]
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set AT91_SDRAMC_NB_4 [expr {1 << 4}]
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set AT91_SDRAMC_CAS [expr {3 << 5}] ;# CAS Latency
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set AT91_SDRAMC_CAS_1 [expr {1 << 5}]
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set AT91_SDRAMC_CAS_2 [expr {2 << 5}]
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set AT91_SDRAMC_CAS_3 [expr {3 << 5}]
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set AT91_SDRAMC_DBW [expr {1 << 7}] ;# Data Bus Width
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set AT91_SDRAMC_DBW_32 [expr {0 << 7}]
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set AT91_SDRAMC_DBW_16 [expr {1 << 7}]
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set AT91_SDRAMC_TWR [expr {0xf << 8}] ;# Write Recovery Delay
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set AT91_SDRAMC_TRC [expr {0xf << 12}] ;# Row Cycle Delay
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set AT91_SDRAMC_TRP [expr {0xf << 16}] ;# Row Precharge Delay
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set AT91_SDRAMC_TRCD [expr {0xf << 20}] ;# Row to Column Delay
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set AT91_SDRAMC_TRAS [expr {0xf << 24}] ;# Active to Precharge Delay
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set AT91_SDRAMC_TXSR [expr {0xf << 28}] ;# Exit Self Refresh to Active Delay
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set AT91_SDRAMC_LPR [expr {$AT91_SDRAMC + 0x10}] ;# SDRAM Controller Low Power Register
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set AT91_SDRAMC_LPCB [expr {3 << 0}] ;# Low-power Configurations
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set AT91_SDRAMC_LPCB_DISABLE 0
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set AT91_SDRAMC_LPCB_SELF_REFRESH 1
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set AT91_SDRAMC_LPCB_POWER_DOWN 2
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set AT91_SDRAMC_LPCB_DEEP_POWER_DOWN 3
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set AT91_SDRAMC_PASR [expr {7 << 4}] ;# Partial Array Self Refresh
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set AT91_SDRAMC_TCSR [expr {3 << 8}] ;# Temperature Compensated Self Refresh
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set AT91_SDRAMC_DS [expr {3 << 10}] ;# Drive Strength
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set AT91_SDRAMC_TIMEOUT [expr {3 << 12}] ;# Time to define when Low Power Mode is enabled
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set AT91_SDRAMC_TIMEOUT_0_CLK_CYCLES [expr {0 << 12}]
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set AT91_SDRAMC_TIMEOUT_64_CLK_CYCLES [expr {1 << 12}]
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set AT91_SDRAMC_TIMEOUT_128_CLK_CYCLES [expr {2 << 12}]
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set AT91_SDRAMC_IER [expr {$AT91_SDRAMC + 0x14}] ;# SDRAM Controller Interrupt Enable Register
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set AT91_SDRAMC_IDR [expr {$AT91_SDRAMC + 0x18}] ;# SDRAM Controller Interrupt Disable Register
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set AT91_SDRAMC_IMR [expr {$AT91_SDRAMC + 0x1C}] ;# SDRAM Controller Interrupt Mask Register
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set AT91_SDRAMC_ISR [expr {$AT91_SDRAMC + 0x20}] ;# SDRAM Controller Interrupt Status Register
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set AT91_SDRAMC_RES [expr {1 << 0}] ;# Refresh Error Status
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set AT91_SDRAMC_MDR [expr {$AT91_SDRAMC + 0x24}] ;# SDRAM Memory Device Register
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set AT91_SDRAMC_MD [expr {3 << 0}] ;# Memory Device Type
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set AT91_SDRAMC_MD_SDRAM 0
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set AT91_SDRAMC_MD_LOW_POWER_SDRAM 1
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