mirror of
https://git.code.sf.net/p/openocd/code
synced 2024-11-25 15:46:25 +00:00
573a39b36c
For historical reasons, no license information was added to the
tcl files. This makes trivial adding the SPDX tag through script:
fgrep -rL SPDX tcl | while read a;do \
sed -i '1{i# SPDX-License-Identifier: GPL-2.0-or-later\n
}' $a;done
With no specific license information from the author, let's extend
the OpenOCD project license GPL-2.0-or-later to the files.
Change-Id: Ief3da306a6e1978de7dfb8f552f9ff23151f9944
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7030
Tested-by: jenkins
131 lines
3.7 KiB
Tcl
131 lines
3.7 KiB
Tcl
# SPDX-License-Identifier: GPL-2.0-or-later
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source [find bitsbytes.tcl]
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source [find cpu/arm/arm7tdmi.tcl]
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source [find memory.tcl]
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source [find mmr_helpers.tcl]
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set CHIP_MAKER atmel
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set CHIP_FAMILY at91sam7
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set CHIP_NAME at91sam7x128
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# how many flash regions.
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set N_FLASH 1
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set FLASH(0,CHIPSELECT) -1
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set FLASH(0,BASE) 0x00100000
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set FLASH(0,LEN) $__128K
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set FLASH(0,HUMAN) "internal flash"
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set FLASH(0,TYPE) "flash"
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set FLASH(0,RWX) $RWX_R_X
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set FLASH(0,ACCESS_WIDTH) $ACCESS_WIDTH_ANY
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# how many ram regions.
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set N_RAM 1
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set RAM(0,CHIPSELECT) -1
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set RAM(0,BASE) 0x00200000
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set RAM(0,LEN) $__32K
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set RAM(0,HUMAN) "internal ram"
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set RAM(0,TYPE) "ram"
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set RAM(0,RWX) $RWX_RWX
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set RAM(0,ACCESS_WIDTH) $ACCESS_WIDTH_ANY
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# I AM LAZY... I create 1 region for all MMRs.
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set N_MMREGS 1
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set MMREGS(0,CHIPSELECT) -1
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set MMREGS(0,BASE) 0xfff00000
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set MMREGS(0,LEN) 0x000fffff
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set MMREGS(0,HUMAN) "mm-regs"
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set MMREGS(0,TYPE) "mmr"
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set MMREGS(0,RWX) $RWX_RW
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set MMREGS(0,ACCESS_WIDTH) $ACCESS_WIDTH_ANY
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# no external memory
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set N_XMEM 0
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set AT91C_BASE_SYS 0xFFFFF000
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set AT91C_BASE_AIC 0xFFFFF000
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set AT91C_BASE_PDC_DBGU 0xFFFFF300
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set AT91C_BASE_DBGU 0xFFFFF200
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set AT91C_BASE_PIOA 0xFFFFF400
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set AT91C_BASE_PIOB 0xFFFFF600
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set AT91C_BASE_CKGR 0xFFFFFC20
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set AT91C_BASE_PMC 0xFFFFFC00
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set AT91C_BASE_RSTC 0xFFFFFD00
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set AT91C_BASE_RTTC 0xFFFFFD20
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set AT91C_BASE_PITC 0xFFFFFD30
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set AT91C_BASE_WDTC 0xFFFFFD40
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set AT91C_BASE_VREG 0xFFFFFD60
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set AT91C_BASE_MC 0xFFFFFF00
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set AT91C_BASE_PDC_SPI1 0xFFFE4100
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set AT91C_BASE_SPI1 0xFFFE4000
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set AT91C_BASE_PDC_SPI0 0xFFFE0100
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set AT91C_BASE_SPI0 0xFFFE0000
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set AT91C_BASE_PDC_US1 0xFFFC4100
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set AT91C_BASE_US1 0xFFFC4000
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set AT91C_BASE_PDC_US0 0xFFFC0100
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set AT91C_BASE_US0 0xFFFC0000
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set AT91C_BASE_PDC_SSC 0xFFFD4100
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set AT91C_BASE_SSC 0xFFFD4000
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set AT91C_BASE_TWI 0xFFFB8000
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set AT91C_BASE_PWMC_CH3 0xFFFCC260
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set AT91C_BASE_PWMC_CH2 0xFFFCC240
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set AT91C_BASE_PWMC_CH1 0xFFFCC220
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set AT91C_BASE_PWMC_CH0 0xFFFCC200
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set AT91C_BASE_PWMC 0xFFFCC000
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set AT91C_BASE_UDP 0xFFFB0000
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set AT91C_BASE_TC0 0xFFFA0000
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set AT91C_BASE_TC1 0xFFFA0040
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set AT91C_BASE_TC2 0xFFFA0080
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set AT91C_BASE_TCB 0xFFFA0000
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set AT91C_BASE_CAN_MB0 0xFFFD0200
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set AT91C_BASE_CAN_MB1 0xFFFD0220
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set AT91C_BASE_CAN_MB2 0xFFFD0240
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set AT91C_BASE_CAN_MB3 0xFFFD0260
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set AT91C_BASE_CAN_MB4 0xFFFD0280
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set AT91C_BASE_CAN_MB5 0xFFFD02A0
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set AT91C_BASE_CAN_MB6 0xFFFD02C0
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set AT91C_BASE_CAN_MB7 0xFFFD02E0
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set AT91C_BASE_CAN 0xFFFD0000
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set AT91C_BASE_EMAC 0xFFFDC000
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set AT91C_BASE_PDC_ADC 0xFFFD8100
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set AT91C_BASE_ADC 0xFFFD8000
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set AT91C_ID(0) FIQ
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set AT91C_ID(1) SYS
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set AT91C_ID(2) PIOA
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set AT91C_ID(3) PIOB
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set AT91C_ID(4) SPI0
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set AT91C_ID(5) SPI1
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set AT91C_ID(6) US0
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set AT91C_ID(7) US1
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set AT91C_ID(8) SSC
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set AT91C_ID(9) TWI
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set AT91C_ID(10) PWMC
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set AT91C_ID(11) UDP
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set AT91C_ID(12) TC0
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set AT91C_ID(13) TC1
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set AT91C_ID(14) TC2
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set AT91C_ID(15) CAN
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set AT91C_ID(16) EMAC
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set AT91C_ID(17) ADC
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set AT91C_ID(18) ""
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set AT91C_ID(19) ""
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set AT91C_ID(20) ""
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set AT91C_ID(21) ""
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set AT91C_ID(22) ""
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set AT91C_ID(23) ""
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set AT91C_ID(24) ""
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set AT91C_ID(25) ""
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set AT91C_ID(26) ""
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set AT91C_ID(27) ""
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set AT91C_ID(28) ""
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set AT91C_ID(29) ""
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set AT91C_ID(30) IRQ0
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set AT91C_ID(31) IRQ1
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source [find chip/atmel/at91/aic.tcl]
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source [find chip/atmel/at91/usarts.tcl]
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source [find chip/atmel/at91/pmc.tcl]
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source [find chip/atmel/at91/rtt.tcl]
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