mirror of
https://git.code.sf.net/p/openocd/code
synced 2024-11-22 04:56:28 +00:00
151b743714
This change implements the support for the ARM Debug Interface v6. The DAP-level interface properly selects the DP Banks and AP address. Sample ARM configuration DAP and JTAG scripts have been updated. Change-Id: I7df87ef764bca587697c778810443649a7f46c2b Signed-off-by: Jacek Wuwer <jacekmw8@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/8067 Tested-by: jenkins Reviewed-by: Ian Thompson <ianst@cadence.com> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
31 lines
751 B
INI
31 lines
751 B
INI
# SPDX-License-Identifier: GPL-2.0-or-later
|
|
# Cadence virtual debug interface
|
|
# Arm Cortex A53x2 through DAP
|
|
|
|
source [find interface/vdebug.cfg]
|
|
|
|
set CORES 2
|
|
set CHIPNAME a53
|
|
set ACCESSPORT 0
|
|
set MEMSTART 0x00000000
|
|
set MEMSIZE 0x1000000
|
|
set DBGBASE {0x80810000 0x80910000}
|
|
set CTIBASE {0x80820000 0x80920000}
|
|
|
|
# vdebug select transport
|
|
transport select dapdirect_swd
|
|
|
|
# JTAG reset config, frequency and reset delay
|
|
adapter speed 50000
|
|
adapter srst delay 5
|
|
|
|
# BFM hierarchical path and input clk period
|
|
vdebug bfm_path tbench.u_vd_swdp_bfm 10ns
|
|
|
|
# DMA Memories to access backdoor (up to 20)
|
|
vdebug mem_path tbench.u_memory.mem_array $MEMSTART $MEMSIZE
|
|
|
|
swd newdap $CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf
|
|
|
|
source [find target/vd_aarch64.cfg]
|