mirror of
https://git.code.sf.net/p/openocd/code
synced 2025-11-04 15:09:11 +00:00
4157732bd8
For historical reasons, no license information was added to the
tcl files. This makes trivial adding the SPDX tag through script:
fgrep -rL SPDX tcl/board | while read a;do \
sed -i '1{i# SPDX-License-Identifier: GPL-2.0-or-later\n
}' $a;done
With no specific license information from the author, let's extend
the OpenOCD project license GPL-2.0-or-later to the files.
Change-Id: Ibcf7da62e842aafd036a78db9ea2b9f11f79af16
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7028
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
161 lines
4.6 KiB
INI
161 lines
4.6 KiB
INI
# SPDX-License-Identifier: GPL-2.0-or-later
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# -------------------------------------------------------------------------
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# KaRo TX25 CPU Module on a StarterkitV base board
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# http://www.karo-electronics.com/tx25.html
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# -------------------------------------------------------------------------
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source [find target/imx25.cfg]
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#-------------------------------------------------------------------------
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# Declare Nand
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#-------------------------------------------------------------------------
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nand device K9F1G08UOC mxc imx25.cpu mx25 hwecc biswap
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$_TARGETNAME configure -event gdb-attach { reset init }
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$_TARGETNAME configure -event reset-init { tx25_init }
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proc tx25_init { } {
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#-------------------------------------------------------------------------
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# AIPS setup - Only setup MPROTx registers. The PACR default values are good.
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# Set all MPROTx to be non-bufferable, trusted for R/W,
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# not forced to user-mode.
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#-------------------------------------------------------------------------
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mww 0x43f00000 0x77777777
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mww 0x43f00004 0x77777777
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mww 0x53f00000 0x77777777
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mww 0x53f00004 0x77777777
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sleep 100
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#-------------------------------------------------------------------------
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# MAX (Multi-Layer AHB Crossbar Switch) setup
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# MPR - priority for MX25 is (SDHC2/SDMA)>USBOTG>RTIC>IAHB>DAHB
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#-------------------------------------------------------------------------
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mww 0x43f04000 0x00043210
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mww 0x43f04100 0x00043210
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mww 0x43f04200 0x00043210
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mww 0x43f04300 0x00043210
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mww 0x43f04400 0x00043210
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# SGPCR - always park on last master
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mww 0x43f04010 0x10
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mww 0x43f04110 0x10
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mww 0x43f04210 0x10
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mww 0x43f04310 0x10
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mww 0x43f04410 0x10
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# MGPCR - restore default values
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mww 0x43f04800 0x0
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mww 0x43f04900 0x0
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mww 0x43f04a00 0x0
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mww 0x43f04b00 0x0
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mww 0x43f04c00 0x0
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# Configure M3IF registers
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# M3IF Control Register (M3IFCTL) for MX25
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# MRRP[0] = LCDC on priority list (1 << 0) = 0x00000001
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# MRRP[1] = MAX1 not on priority list (0 << 1) = 0x00000000
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# MRRP[2] = MAX0 not on priority list (0 << 2) = 0x00000000
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# MRRP[3] = USB HOST not on priority list (0 << 3) = 0x00000000
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# MRRP[4] = SDMA not on priority list (0 << 4) = 0x00000000
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# MRRP[5] = SD/ATA/FEC not on priority list (0 << 5) = 0x00000000
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# MRRP[6] = SCMFBC not on priority list (0 << 6) = 0x00000000
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# MRRP[7] = CSI not on priority list (0 << 7) = 0x00000000
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# ----------
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# 0x00000001
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mww 0xb8003000 0x00000001
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#-------------------------------------------------------------------------
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# configure ARM CLK
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#-------------------------------------------------------------------------
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# Set the Clock CTL (HRM p. 355)
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mww 0x53F80008 0x20034000
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# Setup Clock Gating CTL 0-2 (HRM p. 357)
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mww 0x53F8000C 0x1fffffff
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mww 0x53F80010 0xffffffff
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mww 0x53F80014 0x000fdfff
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#-------------------------------------------------------------------------
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# SDRAM initialization
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#-------------------------------------------------------------------------
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# set to 3.3v SDRAM
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mww 0x43FAC454 0x00000800
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# reset (set up ESDMISC)
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mww 0xB8001010 0x00000002
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# Setup for SDRAM Bank 0
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#-------------------------------------------------------------------------
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# Write ESDCFG0
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mww 0xB8001004 0x00095728
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# CTL SMode = Precharge command
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mww 0xB8001000 0x92116480
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mww 0x80000400 0x00000000
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# CTL SMode = Auto Refresh command
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mww 0xB8001000 0xA2116480
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mww 0x80000000 0x0
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mww 0x80000000 0x0
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mww 0x80000000 0x0
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mww 0x80000000 0x0
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mww 0x80000000 0x0
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mww 0x80000000 0x0
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mww 0x80000000 0x0
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mww 0x80000000 0x0
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# CTL SMode = Load Mode Register command
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mww 0xB8001000 0xB2116480
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mwb 0x80000033 0x00
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# CTL SMode = normal
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mww 0xB8001000 0x82116480
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# Setup for SDRAM Bank 1
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#-------------------------------------------------------------------------
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# Write ESDCFG1
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mww 0xB800100C 0x00095728
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# CTL SMode = Precharge command
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mww 0xB8001008 0x92116480
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mww 0x90000400 0x00000000
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# CTL SMode = Auto Refresh command
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mww 0xB8001008 0xA2116480
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mww 0x90000000 0x00000000
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mww 0x90000000 0x00000000
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mww 0x90000000 0x00000000
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mww 0x90000000 0x00000000
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mww 0x90000000 0x00000000
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mww 0x90000000 0x00000000
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mww 0x90000000 0x00000000
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mww 0x90000000 0x00000000
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# CTL SMode = Load Mode Register command
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mww 0xB8001008 0xB2116480
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mwb 0x90000033 0x00
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# CTL SMode = normal
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mww 0xB8001008 0x82116480
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# GPIO configuration
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#-------------------------------------------------------------------------
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mww 0x43FAC02C 0x00000015
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mww 0x53FD0000 0x01000000
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mww 0x53FD0004 0x00000080
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}
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