mirror of
https://git.code.sf.net/p/openocd/code
synced 2024-11-22 03:46:27 +00:00
4157732bd8
For historical reasons, no license information was added to the
tcl files. This makes trivial adding the SPDX tag through script:
fgrep -rL SPDX tcl/board | while read a;do \
sed -i '1{i# SPDX-License-Identifier: GPL-2.0-or-later\n
}' $a;done
With no specific license information from the author, let's extend
the OpenOCD project license GPL-2.0-or-later to the files.
Change-Id: Ibcf7da62e842aafd036a78db9ea2b9f11f79af16
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7028
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
122 lines
2.8 KiB
INI
122 lines
2.8 KiB
INI
# SPDX-License-Identifier: GPL-2.0-or-later
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######################################
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# Target: Toshiba TOPAS910 -- TMPA910 Starterkit
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#
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######################################
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# We add to the minimal configuration.
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source [find target/tmpa910.cfg]
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######################
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# Target configuration
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######################
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#$_TARGETNAME configure -event gdb-attach { reset init }
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$_TARGETNAME configure -event reset-init { topas910_init }
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proc topas910_init { } {
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# Init PLL
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# my settings
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mww 0xf005000c 0x00000007
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mww 0xf0050010 0x00000065
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mww 0xf005000c 0x000000a7
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sleep 10
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mdw 0xf0050008
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mww 0xf0050008 0x00000002
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mww 0xf0050004 0x00000000
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# NEW: set CLKCR5
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mww 0xf0050054 0x00000040
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#
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sleep 10
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# Init SDRAM
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# _PMCDRV = 0x00000071;
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# //
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# // Initialize SDRAM timing parameter
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# //
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# _DMC_CAS_LATENCY = 0x00000006;
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# _DMC_T_DQSS = 0x00000000;
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# _DMC_T_MRD = 0x00000002;
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# _DMC_T_RAS = 0x00000007;
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#
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# _DMC_T_RC = 0x0000000A;
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# _DMC_T_RCD = 0x00000013;
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#
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# _DMC_T_RFC = 0x0000010A;
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#
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# _DMC_T_RP = 0x00000013;
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# _DMC_T_RRD = 0x00000002;
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# _DMC_T_WR = 0x00000002;
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# _DMC_T_WTR = 0x00000001;
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# _DMC_T_XP = 0x0000000A;
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# _DMC_T_XSR = 0x0000000B;
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# _DMC_T_ESR = 0x00000014;
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#
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# //
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# // Configure SDRAM type parameter
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# _DMC_MEMORY_CFG = 0x00008011;
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# _DMC_USER_CONFIG = 0x00000011;
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# // 32 bit memory interface
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#
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#
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# _DMC_REFRESH_PRD = 0x00000A60;
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# _DMC_CHIP_0_CFG = 0x000140FC;
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#
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# _DMC_DIRECT_CMD = 0x000C0000;
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# _DMC_DIRECT_CMD = 0x00000000;
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#
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# _DMC_DIRECT_CMD = 0x00040000;
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# _DMC_DIRECT_CMD = 0x00040000;
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# _DMC_DIRECT_CMD = 0x00080031;
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# //
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# // Finally start SDRAM
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# //
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# _DMC_MEMC_CMD = MEMC_CMD_GO;
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# */
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mww 0xf0020260 0x00000071
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mww 0xf4300014 0x00000006
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mww 0xf4300018 0x00000000
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mww 0xf430001C 0x00000002
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mww 0xf4300020 0x00000007
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mww 0xf4300024 0x0000000A
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mww 0xf4300028 0x00000013
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mww 0xf430002C 0x0000010A
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mww 0xf4300030 0x00000013
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mww 0xf4300034 0x00000002
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mww 0xf4300038 0x00000002
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mww 0xf430003C 0x00000001
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mww 0xf4300040 0x0000000A
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mww 0xf4300044 0x0000000B
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mww 0xf4300048 0x00000014
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mww 0xf430000C 0x00008011
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mww 0xf4300304 0x00000011
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mww 0xf4300010 0x00000A60
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mww 0xf4300200 0x000140FC
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mww 0xf4300008 0x000C0000
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mww 0xf4300008 0x00000000
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mww 0xf4300008 0x00040000
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mww 0xf4300008 0x00040000
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mww 0xf4300008 0x00080031
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mww 0xf4300004 0x00000000
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sleep 10
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# adapter speed NNNN
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# remap off in case of IROM boot
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mww 0xf0000004 0x00000001
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}
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# comment the following out if usinf J-Link, it soes not support DCC
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arm7_9 dcc_downloads enable ;# Enable faster DCC downloads
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#####################
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# Flash configuration
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#####################
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#flash bank <name> cfi <base> <size> <chip width> <bus width> <target>
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set _FLASHNAME $_CHIPNAME.flash
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flash bank $_FLASHNAME cfi 0x20000000 0x2000000 2 2 $_TARGETNAME
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