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https://git.code.sf.net/p/openocd/code
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34ec5536c0
The STLink API that supports dap-direct is available from STLink firmware v2j24, published in early 2015. We can reasonably expect that any old STLink still in use today has got at least one firmware update during the last 10 years. Most of the board files in upstream OpenOCD still use the STLink in HLA mode. This limits the test coverage of the dap-direct code, which was introduced in OpenOCD v0.11.0. - Rename interface/stlink.cfg as interface/stlink-hla.cfg to still provide support for HLA, adding a deprecated message. - Rename interface/stlink-dap.cfg as interface/stlink.cfg to make dap-direct the default trasport. - Add a redirect file interface/stlink-dap.cfg for users that have out-of-tree custom board files. - Update all the board files to the new setup. - Remove STLink HLA mentions from the documentation, while adding a reference to interface/stlink-hla.cfg Checkpatch-ignore: LONG_LINE Change-Id: I99366bb03cd3b83f8f408514e657f30e59813063 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/8523 Tested-by: jenkins Reviewed-by: Andrzej Sierżęga <asier70@gmail.com>
133 lines
5.7 KiB
INI
133 lines
5.7 KiB
INI
# SPDX-License-Identifier: GPL-2.0-or-later
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# This is a STM32L4P5G discovery board with a single STM32L4R9AGI6 chip.
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# http://www.st.com/en/evaluation-tools/stm32l4p5g-dk.html
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# This is for using the onboard STLINK
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source [find interface/stlink.cfg]
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transport select dapdirect_swd
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# increase working area to 96KB
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set WORKAREASIZE 0x18000
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# enable stmqspi
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set OCTOSPI1 1
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set OCTOSPI2 0
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source [find target/stm32l4x.cfg]
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# OCTOSPI initialization
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# octo: 8-line mode
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proc octospi_init { octo } {
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global a b
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mmw 0x4002104C 0x001001FF 0 ;# RCC_AHB2ENR |= OSPIMEN, GPIOAEN-GPIOIEN (enable clocks)
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mmw 0x40021050 0x00000300 0 ;# RCC_AHB3ENR |= OSPI2EN, OSPI1EN (enable clocks)
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mmw 0x40021058 0x10000000 0 ;# RCC_APB1ENR1 |= PWREN (enable clock)
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sleep 1 ;# Wait for clock startup
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mmw 0x40007004 0x00000200 0 ;# PWR_CR2 |= IOSV (required for use of GPOIG, cf. RM0432)
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mww 0x50061C04 0x07050333 ;# OCTOSPIM_P1CR: assign Port 1 to OCTOSPI2
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mww 0x50061C08 0x03010111 ;# OCTOSPIM_P2CR: assign Port 2 to OCTOSPI1
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# PE11: P1_NCS, PE10: P1_CLK, PG06: P1_DQS, PD07: P1_IO7, PC03: P1_IO6, PD05: P1_IO5
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# PD04: P1_IO4, PA06: P1_IO3, PA07: P1_IO2, PE13: P1_IO1, PE11: P1_IO0
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# PA07:AF10:V, PA06:AF10:V, PC03:AF10:V, PD07:AF10:V, PD05:AF10:V, PD04:AF10:V
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# PE13:AF10:V, PE12:AF10:V, PE11:AF10:V, PE10:AF10:V, PG06:AF03:V
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# Port A: PA07:AF10:V, PA06:AF10:V
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mmw 0x48000000 0x0000A000 0x00005000 ;# MODER
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mmw 0x48000008 0x0000F000 0x00000000 ;# OSPEEDR
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mmw 0x4800000C 0x00000000 0x0000F000 ;# PUPDR
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mmw 0x48000020 0xAA000000 0x55000000 ;# AFRL
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# Port C: PC03:AF10:V
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mmw 0x48000800 0x00000080 0x00000040 ;# MODER
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mmw 0x48000808 0x000000C0 0x00000000 ;# OSPEEDR
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mmw 0x4800080C 0x00000000 0x000000C0 ;# PUPDR
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mmw 0x48000820 0x0000A000 0x00005000 ;# AFRL
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# Port D: PD07:AF10:V, PD05:AF10:V, PD04:AF10:V
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mmw 0x48000C00 0x00008A00 0x00004500 ;# MODER
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mmw 0x48000C08 0x0000CF00 0x00000000 ;# OSPEEDR
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mmw 0x48000C0C 0x00000000 0x0000CF00 ;# PUPDR
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mmw 0x48000C20 0xA0AA0000 0x50550000 ;# AFRL
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# Port E: PE13:AF10:V, PE12:AF10:V, PE11:AF10:V, PE10:AF10:V
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mmw 0x48001000 0x0AA00000 0x05500000 ;# MODER
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mmw 0x48001008 0x0FF00000 0x00000000 ;# OSPEEDR
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mmw 0x4800100C 0x00000000 0x0FF00000 ;# PUPDR
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mmw 0x48001024 0x00AAAA00 0x00555500 ;# AFRH
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# Port G: PG06:AF03:V
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mmw 0x48001800 0x00002000 0x00001000 ;# MODER
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mmw 0x48001808 0x00003000 0x00000000 ;# OSPEEDR
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mmw 0x4800180C 0x00000000 0x00003000 ;# PUPDR
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mmw 0x48001820 0x03000000 0x0C000000 ;# AFRL
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# PG12: P2_NCS, PF04: P2_CLK, PF12: P2_DQS, PG10: P2_IO7, PG09: P2_IO6, PG01: P2_IO5
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# PG00: P2_IO4, PF03: P2_IO3, PF02: P2_IO2, PF01: P2_IO1, PF00: P2_IO0
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# PF12:AF05:V, PF04:AF05:V, PF03:AF05:V, PF02:AF05:V, PF01:AF05:V, PF00:AF05:V
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# PG12:AF05:V, PG10:AF05:V, PG09:AF05:V, PG01:AF05:V, PG00:AF05:V
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# Port F: PF12:AF05:V, PF04:AF05:V, PF03:AF05:V, PF02:AF05:V, PF01:AF05:V, PF00:AF05:V
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mmw 0x48001400 0x020002AA 0x01000155 ;# MODER
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mmw 0x48001408 0x030003FF 0x00000000 ;# OSPEEDR
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mmw 0x4800140C 0x00000000 0x030003FF ;# PUPDR
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mmw 0x48001420 0x00055555 0x000AAAAA ;# AFRL
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mmw 0x48001424 0x00050000 0x000A0000 ;# AFRH
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# Port G: PG12:AF05:V, PG10:AF05:V, PG09:AF05:V, PG01:AF05:V, PG00:AF05:V
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mmw 0x48001800 0x0228000A 0x01140005 ;# MODER
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mmw 0x48001808 0x033C000F 0x00000000 ;# OSPEEDR
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mmw 0x4800180C 0x00000000 0x033C000F ;# PUPDR
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mmw 0x48001820 0x00000055 0x000000AA ;# AFRL
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mmw 0x48001824 0x00050550 0x000A0AA0 ;# AFRH
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# OCTOSPI1: memory-mapped 1-line read mode with 4-byte addresses
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mww 0xA0001130 0x00001000 ;# OCTOSPI_LPTR: deactivate CS after 4096 clocks when FIFO is full
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mww 0xA0001000 0x3040000B ;# OCTOSPI_CR: FMODE=0x1, APMS=1, FTHRES=0, FSEL=0, DQM=0, TCEN=0
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mww 0xA0001008 0x01190100 ;# OCTOSPI_DCR1: MTYP=0x1, FSIZE=0x19, CSHT=0x01, CKMODE=0, DLYBYP=0
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mww 0xA000100C 0x00000001 ;# OCTOSPI_DCR2: PRESCALER=1
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mww 0xA0001108 0x00000000 ;# OCTOSPI_TCR: SSHIFT=0, DHQC=0, DCYC=0x0
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mww 0xA0001100 0x01003101 ;# OCTOSPI_CCR: DMODE=0x1, ABMODE=0x0, ADSIZE=0x3, ADMODE=0x1, ISIZE=0x0, IMODE=0x1
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mww 0xA0001110 0x00000013 ;# OCTOSPI_IR: INSTR=READ4B
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if { $octo == 1 } {
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stmqspi cmd $a 1 0x71 0x00 0x00 0x00 0x00 ;# Read Conf. Reg. 2, addr 0x00000000: DOPI, SOPI bits
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stmqspi cmd $a 0 0x06 ;# Write Enable
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stmqspi cmd $a 1 0x05 ;# Read Status Register
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stmqspi cmd $a 0 0x72 0x00 0x00 0x00 0x00 0x02 ;# Write Conf. Reg. 2, addr 0x00000000: DTR OPI enable
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# OCTOSPI1: memory-mapped 8-line read mode with 4-byte addresses
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mww 0xA0001000 0x3040000B ;# OCTOSPI_CR: FMODE=0x3, APMS=1, FTHRES=0, FSEL=0, DQM=0, TCEN=1, EN=1
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mww 0xA0001108 0x10000006 ;# OCTOSPI_TCR: SSHIFT=0, DHQC=1, DCYC=0x6
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mww 0xA0001100 0x2C003C1C ;# OCTOSPI_CCR: DTR, DMODE=0x4, ABMODE=0x0, ADSIZE=0x3, ADMODE=0x4, ISIZE=0x1, IMODE=0x4
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mww 0xA0001110 0x0000EE11 ;# OCTOSPI_IR: INSTR=OCTA DTR Read
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flash probe $a ;# reload configuration from CR, TCR, CCR, IR register values
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stmqspi cmd $a 0 0x06 ;# Write Enable
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stmqspi cmd $a 1 0x05 0x00 0x00 0x00 0x00 ;# Read Status Register (note dummy address in 8-line mode)
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stmqspi cmd $a 0 0x04 ;# Write Disable
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stmqspi cmd $a 1 0x05 0x00 0x00 0x00 0x00 ;# Read Status Register (note dummy address in 8-line mode)
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stmqspi cmd $a 1 0x71 0x00 0x00 0x00 0x00 ;# Read Conf. Reg. 2, addr 0x00000000: DOPI, SOPI bits
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}
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}
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$_TARGETNAME configure -event reset-init {
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mmw 0x40022000 0x00000003 0x0000000C ;# 3 WS for 72 MHz HCLK
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sleep 1
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mmw 0x40021000 0x00000100 0x00000000 ;# HSI on
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mww 0x4002100C 0x01002432 ;# RCC_PLLCFGR 72 MHz: PLLREN=1, PLLM=4, PLLN=36, PLLR=2, HSI
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mww 0x40021008 0x00008001 ;# always HSI, APB1: /1, APB2: /1
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mmw 0x40021000 0x01000000 0x00000000 ;# PLL on
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sleep 1
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mmw 0x40021008 0x00000003 0x00000000 ;# switch to PLL
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sleep 1
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adapter speed 24000
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octospi_init 1
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}
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