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https://git.code.sf.net/p/openocd/code
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34ec5536c0
The STLink API that supports dap-direct is available from STLink firmware v2j24, published in early 2015. We can reasonably expect that any old STLink still in use today has got at least one firmware update during the last 10 years. Most of the board files in upstream OpenOCD still use the STLink in HLA mode. This limits the test coverage of the dap-direct code, which was introduced in OpenOCD v0.11.0. - Rename interface/stlink.cfg as interface/stlink-hla.cfg to still provide support for HLA, adding a deprecated message. - Rename interface/stlink-dap.cfg as interface/stlink.cfg to make dap-direct the default trasport. - Add a redirect file interface/stlink-dap.cfg for users that have out-of-tree custom board files. - Update all the board files to the new setup. - Remove STLink HLA mentions from the documentation, while adding a reference to interface/stlink-hla.cfg Checkpatch-ignore: LONG_LINE Change-Id: I99366bb03cd3b83f8f408514e657f30e59813063 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/8523 Tested-by: jenkins Reviewed-by: Andrzej Sierżęga <asier70@gmail.com>
59 lines
2.0 KiB
INI
59 lines
2.0 KiB
INI
# SPDX-License-Identifier: GPL-2.0-or-later
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# This is an STM32L476G discovery board with a single STM32L476VGT6 chip.
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# http://www.st.com/en/evaluation-tools/32l476gdiscovery.html
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# This is for using the onboard STLINK
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source [find interface/stlink.cfg]
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transport select dapdirect_swd
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# increase working area to 96KB
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set WORKAREASIZE 0x18000
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# enable stmqspi
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set QUADSPI 1
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source [find target/stm32l4x.cfg]
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# QUADSPI initialization
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proc qspi_init { } {
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global a
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mmw 0x4002104C 0x000001FF 0 ;# RCC_AHB2ENR |= GPIOAEN-GPIOIEN (enable clocks)
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mmw 0x40021050 0x00000100 0 ;# RCC_AHB3ENR |= QSPIEN (enable clock)
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sleep 1 ;# Wait for clock startup
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# PE11: NCS, PE10: CLK, PE15: BK1_IO3, PE14: BK1_IO2, PE13: BK1_IO1, PE12: BK1_IO0
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# PE15:AF10:V, PE14:AF10:V, PE13:AF10:V, PE12:AF10:V, PE11:AF10:V, PE10:AF10:V
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# Port E: PE15:AF10:V, PE14:AF10:V, PE13:AF10:V, PE12:AF10:V, PE11:AF10:V, PE10:AF10:V
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mmw 0x48001000 0xAAA00000 0x55500000 ;# MODER
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mmw 0x48001008 0xFFF00000 0x00000000 ;# OSPEEDR
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mmw 0x48001024 0xAAAAAA00 0x55555500 ;# AFRH
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mww 0xA0001030 0x00001000 ;# QUADSPI_LPTR: deactivate CS after 4096 clocks when FIFO is full
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mww 0xA0001000 0x01500008 ;# QUADSPI_CR: PRESCALER=1, APMS=1, FTHRES=0, FSEL=0, DFM=0, SSHIFT=0, TCEN=1
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mww 0xA0001004 0x00170100 ;# QUADSPI_DCR: FSIZE=0x17, CSHT=0x01, CKMODE=0
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mmw 0xA0001000 0x00000001 0 ;# QUADSPI_CR: EN=1
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# memory-mapped read mode with 3-byte addresses
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mww 0xA0001014 0x0D002503 ;# QUADSPI_CCR: FMODE=0x3, DMODE=0x1, DCYC=0x0, ADSIZE=0x2, ADMODE=0x1, IMODE=0x1, INSTR=READ
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}
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$_TARGETNAME configure -event reset-init {
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mmw 0x40022000 0x00000004 0x00000003 ;# 4 WS for 72 MHz HCLK
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sleep 1
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mmw 0x40021000 0x00000100 0x00000000 ;# HSI on
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mww 0x4002100C 0x01002432 ;# 72 MHz: PLLREN=1, PLLM=4, PLLN=36, PLLR=2, HSI
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mww 0x40021008 0x00008001 ;# always HSI, APB1: /1, APB2: /1
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mmw 0x40021000 0x01000000 0x00000000 ;# PLL on
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sleep 1
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mmw 0x40021008 0x00000003 0x00000000 ;# switch to PLL
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sleep 1
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adapter speed 4000
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qspi_init
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}
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