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https://git.code.sf.net/p/openocd/code
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34ec5536c0
The STLink API that supports dap-direct is available from STLink firmware v2j24, published in early 2015. We can reasonably expect that any old STLink still in use today has got at least one firmware update during the last 10 years. Most of the board files in upstream OpenOCD still use the STLink in HLA mode. This limits the test coverage of the dap-direct code, which was introduced in OpenOCD v0.11.0. - Rename interface/stlink.cfg as interface/stlink-hla.cfg to still provide support for HLA, adding a deprecated message. - Rename interface/stlink-dap.cfg as interface/stlink.cfg to make dap-direct the default trasport. - Add a redirect file interface/stlink-dap.cfg for users that have out-of-tree custom board files. - Update all the board files to the new setup. - Remove STLink HLA mentions from the documentation, while adding a reference to interface/stlink-hla.cfg Checkpatch-ignore: LONG_LINE Change-Id: I99366bb03cd3b83f8f408514e657f30e59813063 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/8523 Tested-by: jenkins Reviewed-by: Andrzej Sierżęga <asier70@gmail.com>
141 lines
5.6 KiB
INI
141 lines
5.6 KiB
INI
# SPDX-License-Identifier: GPL-2.0-or-later
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# This is a stm32h747i-disco with a single STM32H747XIH6 chip.
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# www.st.com/en/product/stm32h747i-disco.html
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#
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# This is for using the onboard STLINK
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source [find interface/stlink.cfg]
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transport select dapdirect_swd
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set CHIPNAME stm32h747xih6
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# enable stmqspi
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if {![info exists QUADSPI]} {
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set QUADSPI 1
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}
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source [find target/stm32h7x_dual_bank.cfg]
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reset_config srst_only
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# QUADSPI initialization
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# qpi: 4-line mode
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proc qspi_init { qpi } {
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global a
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mmw 0x580244E0 0x000007FF 0 ;# RCC_AHB4ENR |= GPIOAEN-GPIOKEN (enable clocks)
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mmw 0x580244D4 0x00004000 0 ;# RCC_AHB3ENR |= QSPIEN (enable clock)
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sleep 1 ;# Wait for clock startup
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# PG06: BK1_NCS, PB02: CLK, PF06: BK1_IO3, PF07: BK1_IO2, PF09: BK1_IO1, PD11: BK1_IO0,
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# PG14: BK2_IO3, PG09: BK2_IO2, PH03: BK2_IO1, PH02: BK2_IO0
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# PB02:AF09:V, PD11:AF09:V, PF09:AF10:V, PF07:AF09:V, PF06:AF09:V, PG14:AF09:H
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# PG09:AF09:V, PG06:AF10:H, PH03:AF09:V, PH02:AF09:V
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# Port B: PB02:AF09:V
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mmw 0x58020400 0x00000020 0x00000010 ;# MODER
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mmw 0x58020408 0x00000030 0x00000000 ;# OSPEEDR
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mmw 0x58020420 0x00000900 0x00000600 ;# AFRL
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# Port D: PD11:AF09:V
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mmw 0x58020C00 0x00800000 0x00400000 ;# MODER
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mmw 0x58020C08 0x00C00000 0x00000000 ;# OSPEEDR
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mmw 0x58020C24 0x00009000 0x00006000 ;# AFRH
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# Port F: PF09:AF10:V, PF07:AF09:V, PF06:AF09:V
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mmw 0x58021400 0x0008A000 0x00045000 ;# MODER
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mmw 0x58021408 0x000CF000 0x00000000 ;# OSPEEDR
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mmw 0x58021420 0x99000000 0x66000000 ;# AFRL
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mmw 0x58021424 0x000000A0 0x00000050 ;# AFRH
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# Port G: PG14:AF09:H, PG09:AF09:V, PG06:AF10:H
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mmw 0x58021800 0x20082000 0x10041000 ;# MODER
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mmw 0x58021808 0x200C2000 0x10001000 ;# OSPEEDR
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mmw 0x58021820 0x0A000000 0x05000000 ;# AFRL
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mmw 0x58021824 0x09000090 0x06000060 ;# AFRH
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# Port H: PH03:AF09:V, PH02:AF09:V
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mmw 0x58021C00 0x000000A0 0x00000050 ;# MODER
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mmw 0x58021C08 0x000000F0 0x00000000 ;# OSPEEDR
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mmw 0x58021C20 0x00009900 0x00006600 ;# AFRL
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# correct FSIZE is 0x1A, however, this causes trouble when
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# reading the last bytes at end of bank in *memory mapped* mode
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# for dual flash mode 2 * mt25ql512
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mww 0x52005000 0x05500058 ;# QUADSPI_CR: PRESCALER=5, APMS=1, FTHRES=0, FSEL=0, DFM=1, SSHIFT=1, TCEN=1
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mww 0x52005004 0x001A0200 ;# QUADSPI_DCR: FSIZE=0x1A, CSHT=0x02, CKMODE=0
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mww 0x52005030 0x00001000 ;# QUADSPI_LPTR: deactivate CS after 4096 clocks when FIFO is full
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mww 0x52005014 0x0D002503 ;# QUADSPI_CCR: FMODE=0x3, DMODE=0x1, DCYC=0x0, ADSIZE=0x3, ADMODE=0x1, IMODE=0x1
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mmw 0x52005000 0x00000001 0 ;# QUADSPI_CR: EN=1
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# Exit QPI mode
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mmw 0x52005000 0x00000002 0 ;# QUADSPI_CR: ABORT=1
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mww 0x52005014 0x000003F5 ;# QUADSPI_CCR: FMODE=0x0, DMODE=0x0, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x3, INSTR=Exit QPI
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sleep 1
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if { $qpi == 1 } {
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# Write Enable
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mmw 0x52005000 0x00000002 0 ;# QUADSPI_CR: ABORT=1
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mww 0x52005014 0x00000106 ;# QUADSPI_CCR: FMODE=0x0, DMODE=0x0, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x1, INSTR=Write Enable
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sleep 1
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# Configure dummy clocks via volatile configuration register
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mmw 0x52005000 0x00000002 0 ;# QUADSPI_CR: ABORT=1
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mww 0x52005010 0x00000001 ;# QUADSPI_DLR: 2 data bytes
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mww 0x52005014 0x01000181 ;# QUADSPI_CCR: FMODE=0x0, DMODE=0x1, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x1, INSTR=Write Volatile Conf. Reg.
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mwh 0x52005020 0xABAB ;# QUADSPI_DR: 0xAB 0xAB for 10 dummy clocks
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sleep 1
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# Write Enable
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mmw 0x52005000 0x00000002 0 ;# QUADSPI_CR: ABORT=1
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mww 0x52005014 0x00000106 ;# QUADSPI_CCR: FMODE=0x0, DMODE=0x0, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x1, INSTR=Write Enable
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sleep 1
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# Enable QPI mode via enhanced volatile configuration register
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mmw 0x52005000 0x00000002 0 ;# QUADSPI_CR: ABORT=1
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mww 0x52005010 0x00000001 ;# QUADSPI_DLR: 2 data bytes
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mww 0x52005014 0x01000161 ;# QUADSPI_CCR: FMODE=0x0, DMODE=0x1, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x1, INSTR=Write Enhanced Conf. Reg.
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mwh 0x52005020 0x3F3F ;# QUADSPI_DR: 0x3F 0x3F to enable QPI and DPI mode
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sleep 1
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# Enter QPI mode
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mmw 0x52005000 0x00000002 0 ;# QUADSPI_CR: ABORT=1
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mww 0x52005014 0x00000135 ;# QUADSPI_CCR: FMODE=0x0, DMODE=0x0, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x1, INSTR=Enter QPI
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sleep 1
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# memory-mapped fast read mode with 4-byte addresses and 10 dummy cycles (for read only)
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mmw 0x52005000 0x00000002 0 ;# QUADSPI_CR: ABORT=1
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mww 0x52005014 0x0F283FEC ;# QUADSPI_CCR: FMODE=0x3, DMODE=0x3, DCYC=0xA, ADSIZE=0x3, ADMODE=0x3, IMODE=0x3, INSTR=Fast READ
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} else {
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# memory-mapped read mode with 4-byte addresses
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mmw 0x52005000 0x00000002 0 ;# QUADSPI_CR: ABORT=1
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mww 0x52005014 0x0D003513 ;# QUADSPI_CCR: FMODE=0x3, DMODE=0x1, DCYC=0x0, ADSIZE=0x3, ADMODE=0x1, IMODE=0x1, INSTR=READ
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}
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}
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$_CHIPNAME.cpu0 configure -event reset-init {
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global QUADSPI
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mmw 0x52002000 0x00000004 0x0000000B ;# FLASH_ACR: 4 WS for 192 MHZ HCLK
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mmw 0x58024400 0x00000001 0x00000018 ;# RCC_CR: HSIDIV=1, HSI on
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mmw 0x58024410 0x10000000 0xEE000007 ;# RCC_CFGR: MCO2=system, MCO2PRE=8, HSI as system clock
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mww 0x58024418 0x00000040 ;# RCC_D1CFGR: D1CPRE=1, D1PPRE=2, HPRE=1
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mww 0x5802441C 0x00000440 ;# RCC_D2CFGR: D2PPRE2=2, D2PPRE1=2
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mww 0x58024420 0x00000040 ;# RCC_D3CFGR: D3PPRE=2
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mww 0x58024428 0x00000040 ;# RCC_PPLCKSELR: DIVM3=0, DIVM2=0, DIVM1=4, PLLSRC=HSI
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mmw 0x5802442C 0x0001000C 0x00000002 ;# RCC_PLLCFGR: PLL1RGE=8MHz to 16MHz, PLL1VCOSEL=wide
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mww 0x58024430 0x01070217 ;# RCC_PLL1DIVR: 192 MHz: DIVR1=2, DIVQ=8, DIVP1=2, DIVN1=24
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mmw 0x58024400 0x01000000 0 ;# RCC_CR: PLL1ON=1
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sleep 1
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mmw 0x58024410 0x00000003 0 ;# RCC_CFGR: PLL1 as system clock
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sleep 1
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adapter speed 24000
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if { $QUADSPI } {
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qspi_init 1
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}
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}
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