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https://git.code.sf.net/p/openocd/code
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34ec5536c0
The STLink API that supports dap-direct is available from STLink firmware v2j24, published in early 2015. We can reasonably expect that any old STLink still in use today has got at least one firmware update during the last 10 years. Most of the board files in upstream OpenOCD still use the STLink in HLA mode. This limits the test coverage of the dap-direct code, which was introduced in OpenOCD v0.11.0. - Rename interface/stlink.cfg as interface/stlink-hla.cfg to still provide support for HLA, adding a deprecated message. - Rename interface/stlink-dap.cfg as interface/stlink.cfg to make dap-direct the default trasport. - Add a redirect file interface/stlink-dap.cfg for users that have out-of-tree custom board files. - Update all the board files to the new setup. - Remove STLink HLA mentions from the documentation, while adding a reference to interface/stlink-hla.cfg Checkpatch-ignore: LONG_LINE Change-Id: I99366bb03cd3b83f8f408514e657f30e59813063 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/8523 Tested-by: jenkins Reviewed-by: Andrzej Sierżęga <asier70@gmail.com>
50 lines
1.4 KiB
INI
50 lines
1.4 KiB
INI
# SPDX-License-Identifier: GPL-2.0-or-later
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# This is a stm32h745i-disco with a single STM32H745XIH6 chip.
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# www.st.com/en/product/stm32h745i-disco.html
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#
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# This is for using the onboard STLINK
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source [find interface/stlink.cfg]
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transport select dapdirect_swd
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set CHIPNAME stm32h745xih6
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# enable stmqspi
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if {![info exists QUADSPI]} {
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set QUADSPI 1
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}
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source [find target/stm32h7x_dual_bank.cfg]
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reset_config srst_only
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source [find board/stm32h7x_dual_qspi.cfg]
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$_CHIPNAME.cpu0 configure -event reset-init {
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global QUADSPI
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mmw 0x52002000 0x00000004 0x0000000B ;# FLASH_ACR: 4 WS for 192 MHZ HCLK
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mmw 0x58024400 0x00000001 0x00000018 ;# RCC_CR: HSIDIV=1, HSI on
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mmw 0x58024410 0x10000000 0xEE000007 ;# RCC_CFGR: MCO2=system, MCO2PRE=8, HSI as system clock
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mww 0x58024418 0x00000040 ;# RCC_D1CFGR: D1CPRE=1, D1PPRE=2, HPRE=1
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mww 0x5802441C 0x00000440 ;# RCC_D2CFGR: D2PPRE2=2, D2PPRE1=2
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mww 0x58024420 0x00000040 ;# RCC_D3CFGR: D3PPRE=2
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mww 0x58024428 0x00000040 ;# RCC_PPLCKSELR: DIVM3=0, DIVM2=0, DIVM1=4, PLLSRC=HSI
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mmw 0x5802442C 0x0001000C 0x00000002 ;# RCC_PLLCFGR: PLL1RGE=8MHz to 16MHz, PLL1VCOSEL=wide
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mww 0x58024430 0x01070217 ;# RCC_PLL1DIVR: 192 MHz: DIVR1=2, DIVQ=8, DIVP1=2, DIVN1=24
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mmw 0x58024400 0x01000000 0 ;# RCC_CR: PLL1ON=1
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sleep 1
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mmw 0x58024410 0x00000003 0 ;# RCC_CFGR: PLL1 as system clock
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sleep 1
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adapter speed 24000
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if { $QUADSPI } {
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qspi_init 1
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}
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}
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