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https://git.code.sf.net/p/openocd/code
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34ec5536c0
The STLink API that supports dap-direct is available from STLink firmware v2j24, published in early 2015. We can reasonably expect that any old STLink still in use today has got at least one firmware update during the last 10 years. Most of the board files in upstream OpenOCD still use the STLink in HLA mode. This limits the test coverage of the dap-direct code, which was introduced in OpenOCD v0.11.0. - Rename interface/stlink.cfg as interface/stlink-hla.cfg to still provide support for HLA, adding a deprecated message. - Rename interface/stlink-dap.cfg as interface/stlink.cfg to make dap-direct the default trasport. - Add a redirect file interface/stlink-dap.cfg for users that have out-of-tree custom board files. - Update all the board files to the new setup. - Remove STLink HLA mentions from the documentation, while adding a reference to interface/stlink-hla.cfg Checkpatch-ignore: LONG_LINE Change-Id: I99366bb03cd3b83f8f408514e657f30e59813063 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/8523 Tested-by: jenkins Reviewed-by: Andrzej Sierżęga <asier70@gmail.com>
79 lines
2.5 KiB
INI
79 lines
2.5 KiB
INI
# SPDX-License-Identifier: GPL-2.0-or-later
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# This is an STM32F723E discovery board with a single STM32F723IEK6 chip.
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# http://www.st.com/en/evaluation-tools/32f723ediscovery.html
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# This is for using the onboard STLINK
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source [find interface/stlink.cfg]
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transport select dapdirect_swd
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# increase working area to 128KB
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set WORKAREASIZE 0x20000
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# enable stmqspi
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set QUADSPI 1
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source [find target/stm32f7x.cfg]
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reset_config srst_only
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# QUADSPI initialization
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proc qspi_init { } {
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global a
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mmw 0x40023830 0x000007FF 0 ;# RCC_AHB1ENR |= GPIOAEN-GPIOKEN (enable clocks)
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mmw 0x40023838 0x00000002 0 ;# RCC_AHB3ENR |= QSPIEN (enable clock)
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sleep 1 ;# Wait for clock startup
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# PB02: CLK, PB06: BK1_NCS, PD13: BK1_IO3, PE02: BK1_IO2, PC10: BK1_IO1, PC09: BK1_IO0
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# PB06:AF10:V, PB02:AF09:V, PC10:AF09:V, PC09:AF09:V, PD13:AF09:V, PE02:AF09:V
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# Port B: PB06:AF10:V, PB02:AF09:V
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mmw 0x40020400 0x00002020 0x00001010 ;# MODER
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mmw 0x40020408 0x00003030 0x00000000 ;# OSPEEDR
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mmw 0x40020420 0x0A000900 0x05000600 ;# AFRL
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# Port C: PC10:AF09:V, PC09:AF09:V
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mmw 0x40020800 0x00280000 0x00140000 ;# MODER
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mmw 0x40020808 0x003C0000 0x00000000 ;# OSPEEDR
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mmw 0x40020824 0x00000990 0x00000660 ;# AFRH
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# Port D: PD13:AF09:V
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mmw 0x40020C00 0x08000000 0x04000000 ;# MODER
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mmw 0x40020C08 0x0C000000 0x00000000 ;# OSPEEDR
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mmw 0x40020C24 0x00900000 0x00600000 ;# AFRH
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# Port E: PE02:AF09:V
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mmw 0x40021000 0x00000020 0x00000010 ;# MODER
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mmw 0x40021008 0x00000030 0x00000000 ;# OSPEEDR
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mmw 0x40021020 0x00000900 0x00000600 ;# AFRL
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mww 0xA0001030 0x00001000 ;# QUADSPI_LPTR: deactivate CS after 4096 clocks when FIFO is full
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mww 0xA0001000 0x03500008 ;# QUADSPI_CR: PRESCALER=3, APMS=1, FTHRES=0, FSEL=0, DFM=0, SSHIFT=0, TCEN=1
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mww 0xA0001004 0x00190100 ;# QUADSPI_DCR: FSIZE=0x19, CSHT=0x01, CKMODE=0
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mmw 0xA0001000 0x00000001 0 ;# QUADSPI_CR: EN=1
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# 1-line spi mode
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mww 0xA0001014 0x000003F5 ;# QUADSPI_CCR: FMODE=0x0, DMODE=0x0, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x3, INSTR=RSTQIO
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sleep 1
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# memory-mapped read mode with 4-byte addresses
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mww 0xA0001014 0x0D003513 ;# QUADSPI_CCR: FMODE=0x3, DMODE=0x1, DCYC=0x0, ADSIZE=0x3, ADMODE=0x1, IMODE=0x1, INSTR=READ
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}
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$_TARGETNAME configure -event reset-init {
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mww 0x40023C00 0x00000006 ;# 6 WS for 192 MHz HCLK
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sleep 1
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mww 0x40023804 0x24003008 ;# 192 MHz: PLLM=8, PLLN=192, PLLP=2
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mww 0x40023808 0x00009400 ;# APB1: /4, APB2: /2
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mmw 0x40023800 0x01000000 0x00000000 ;# PLL on
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sleep 1
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mmw 0x40023808 0x00000002 0x00000000 ;# switch to PLL
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sleep 1
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adapter speed 4000
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qspi_init
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}
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