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https://git.code.sf.net/p/openocd/code
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34ec5536c0
The STLink API that supports dap-direct is available from STLink firmware v2j24, published in early 2015. We can reasonably expect that any old STLink still in use today has got at least one firmware update during the last 10 years. Most of the board files in upstream OpenOCD still use the STLink in HLA mode. This limits the test coverage of the dap-direct code, which was introduced in OpenOCD v0.11.0. - Rename interface/stlink.cfg as interface/stlink-hla.cfg to still provide support for HLA, adding a deprecated message. - Rename interface/stlink-dap.cfg as interface/stlink.cfg to make dap-direct the default trasport. - Add a redirect file interface/stlink-dap.cfg for users that have out-of-tree custom board files. - Update all the board files to the new setup. - Remove STLink HLA mentions from the documentation, while adding a reference to interface/stlink-hla.cfg Checkpatch-ignore: LONG_LINE Change-Id: I99366bb03cd3b83f8f408514e657f30e59813063 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/8523 Tested-by: jenkins Reviewed-by: Andrzej Sierżęga <asier70@gmail.com>
73 lines
2.4 KiB
INI
73 lines
2.4 KiB
INI
# SPDX-License-Identifier: GPL-2.0-or-later
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# This is an STM32F412G discovery board with a single STM32F412ZGT6 chip.
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# http://www.st.com/en/evaluation-tools/32f412gdiscovery.html
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# This is for using the onboard STLINK
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source [find interface/stlink.cfg]
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transport select dapdirect_swd
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# increase working area to 128KB
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set WORKAREASIZE 0x20000
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# enable stmqspi
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set QUADSPI 1
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source [find target/stm32f4x.cfg]
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# QUADSPI initialization
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proc qspi_init { } {
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global a
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mmw 0x40023830 0x000000FF 0 ;# RCC_AHB1ENR |= GPIOAEN-GPIOHEN (enable clocks)
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mmw 0x40023838 0x00000002 0 ;# RCC_AHB3ENR |= QSPIEN (enable clock)
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sleep 1 ;# Wait for clock startup
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# PB02: CLK, PG06: BK1_NCS, PF06: BK1_IO3, PF07: BK1_IO2, PF09: BK1_IO1, PF08: BK1_IO0
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# PB02:AF09:V, PF09:AF10:V, PF08:AF10:V, PF07:AF09:V, PF06:AF09:V, PG06:AF10:V
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# Port B: PB02:AF09:V
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mmw 0x40020400 0x00000020 0x00000010 ;# MODER
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mmw 0x40020408 0x00000030 0x00000000 ;# OSPEEDR
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mmw 0x40020420 0x00000900 0x00000600 ;# AFRL
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# Port F: PF09:AF10:V, PF08:AF10:V, PF07:AF09:V, PF06:AF09:V
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mmw 0x40021400 0x000AA000 0x00055000 ;# MODER
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mmw 0x40021408 0x000FF000 0x00000000 ;# OSPEEDR
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mmw 0x40021420 0x99000000 0x66000000 ;# AFRL
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mmw 0x40021424 0x000000AA 0x00000055 ;# AFRH
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# Port G: PG06:AF10:V
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mmw 0x40021800 0x00002000 0x00001000 ;# MODER
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mmw 0x40021808 0x00003000 0x00000000 ;# OSPEEDR
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mmw 0x40021820 0x0A000000 0x05000000 ;# AFRL
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mww 0xA0001030 0x00001000 ;# QUADSPI_LPTR: deactivate CS after 4096 clocks when FIFO is full
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mww 0xA0001000 0x03500008 ;# QUADSPI_CR: PRESCALER=3, APMS=1, FTHRES=0, FSEL=0, DFM=0, SSHIFT=0, TCEN=1
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mww 0xA0001004 0x00170100 ;# QUADSPI_DCR: FSIZE=0x17, CSHT=0x01, CKMODE=0
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mmw 0xA0001000 0x00000001 0 ;# QUADSPI_CR: EN=1
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# 1-line spi mode
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mww 0xA0001014 0x000003F5 ;# QUADSPI_CCR: FMODE=0x0, DMODE=0x0, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x3, INSTR=RSTQIO
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sleep 1
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# memory-mapped read mode with 3-byte addresses
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mww 0xA0001014 0x0D002503 ;# QUADSPI_CCR: FMODE=0x3, DMODE=0x1, DCYC=0x0, ADSIZE=0x2, ADMODE=0x1, IMODE=0x1, INSTR=READ
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}
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$_TARGETNAME configure -event reset-init {
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mww 0x40023C00 0x00000003 ;# 3 WS for 96 MHz HCLK
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sleep 1
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mww 0x40023804 0x24001808 ;# 96 MHz: HSI, PLLM=8, PLLN=96, PLLP=2
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mww 0x40023808 0x00001000 ;# APB1: /2, APB2: /1
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mmw 0x40023800 0x01000000 0x00000000 ;# PLL on
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sleep 1
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mmw 0x40023808 0x00000002 0x00000000 ;# switch to PLL
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sleep 1
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adapter speed 4000
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qspi_init
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}
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