mirror of
https://git.code.sf.net/p/openocd/code
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4157732bd8
For historical reasons, no license information was added to the
tcl files. This makes trivial adding the SPDX tag through script:
fgrep -rL SPDX tcl/board | while read a;do \
sed -i '1{i# SPDX-License-Identifier: GPL-2.0-or-later\n
}' $a;done
With no specific license information from the author, let's extend
the OpenOCD project license GPL-2.0-or-later to the files.
Change-Id: Ibcf7da62e842aafd036a78db9ea2b9f11f79af16
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7028
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
54 lines
1.5 KiB
INI
54 lines
1.5 KiB
INI
# SPDX-License-Identifier: GPL-2.0-or-later
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# Configuration for the ST SPEAr310 Evaluation board
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# EVALSPEAr310 Rev. 2.0
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# http://www.st.com/spear
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#
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# Date: 2010-08-17
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# Author: Antonio Borneo <borneo.antonio@gmail.com>
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# The standard board has JTAG SRST not connected.
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# This script targets such boards using quirky code to bypass the issue.
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#
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# Check ST Application Note AN3321 on how to fix SRST on
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# the board, then use the script board/spear310evb20_mod.cfg
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source [find mem_helper.tcl]
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source [find target/spear3xx.cfg]
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source [find chip/st/spear/spear3xx_ddr.tcl]
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source [find chip/st/spear/spear3xx.tcl]
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arm7_9 dcc_downloads enable
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arm7_9 fast_memory_access enable
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# CFI parallel NOR on EMI CS0. 2x 16bit 8M devices = 16Mbyte.
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set _FLASHNAME0 $_CHIPNAME.pnor
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flash bank $_FLASHNAME0 cfi 0x50000000 0x01000000 2 4 $_TARGETNAME
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# Serial NOR on SMI CS0. 8Mbyte.
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set _FLASHNAME1 $_CHIPNAME.snor
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flash bank $_FLASHNAME1 stmsmi 0xf8000000 0 0 0 $_TARGETNAME
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if { [info exists BOARD_HAS_SRST] } {
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# Modified board has SRST on JTAG connector
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reset_config trst_and_srst separate srst_gates_jtag \
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trst_push_pull srst_open_drain
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} else {
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# Standard board has no SRST on JTAG connector
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reset_config trst_only separate srst_gates_jtag trst_push_pull
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source [find chip/st/spear/quirk_no_srst.tcl]
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}
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$_TARGETNAME configure -event reset-init { spear310evb20_init }
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proc spear310evb20_init {} {
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reg pc 0xffff0020 ;# loop forever
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sp3xx_clock_default
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sp3xx_common_init
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sp3xx_ddr_init "mt47h64m16_3_333_cl5_async"
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sp310_init
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sp310_emi_init
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}
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