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https://git.code.sf.net/p/openocd/code
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4157732bd8
For historical reasons, no license information was added to the tcl files. This makes trivial adding the SPDX tag through script: fgrep -rL SPDX tcl/board | while read a;do \ sed -i '1{i# SPDX-License-Identifier: GPL-2.0-or-later\n }' $a;done With no specific license information from the author, let's extend the OpenOCD project license GPL-2.0-or-later to the files. Change-Id: Ibcf7da62e842aafd036a78db9ea2b9f11f79af16 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/7028 Tested-by: jenkins Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
69 lines
1.7 KiB
INI
69 lines
1.7 KiB
INI
# SPDX-License-Identifier: GPL-2.0-or-later
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# Avalue RSC-W8910 sbc
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# http://www.avalue.com.tw/products/RSC-W910.cfm
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# 2MB NOR Flash
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# 64MB SDRAM
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# 128MB NAND Flash
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# Based on Nuvoton nuc910
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source [find target/nuc910.cfg]
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#
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# reset only behaves correctly if we use srst_pulls_trst
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#
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reset_config trst_and_srst srst_pulls_trst
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adapter speed 1000
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adapter srst delay 100
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jtag_ntrst_delay 100
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$_TARGETNAME configure -work-area-phys 0x00000000 -work-area-size 0x04000000 -work-area-backup 0
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set _FLASHNAME $_CHIPNAME.flash
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flash bank $_FLASHNAME cfi 0x20000000 0x00200000 2 2 $_TARGETNAME
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set _NANDNAME $_CHIPNAME.nand
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nand device $_NANDNAME nuc910 $_TARGETNAME
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#
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# Target events
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#
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$_TARGETNAME configure -event reset-start {adapter speed 1000}
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$_TARGETNAME configure -event reset-init {
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# switch on PLL for 200MHz operation
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# running from 15MHz input clock
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mww 0xB0000200 0x00000030 ;# CLKEN
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mww 0xB0000204 0x00000f3c ;# CLKSEL
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mww 0xB0000208 0x05007000 ;# CLKDIV
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mww 0xB000020C 0x00004f24 ;# PLLCON0
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mww 0xB0000210 0x00002b63 ;# PLLCON1
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mww 0xB000000C 0x08817fa6 ;# MFSEL
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sleep 10
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# we are now running @ 200MHz
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# enable all openocd speed tweaks
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arm7_9 dcc_downloads enable
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arm7_9 fast_memory_access enable
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adapter speed 15000
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# map nor flash to 0x20000000
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# map sdram to 0x00000000
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mww 0xb0001000 0x000530c1 ;# EBICON
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mww 0xb0001004 0x40030084 ;# ROMCON
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mww 0xb0001008 0x000010ee ;# SDCONF0
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mww 0xb000100C 0x00000000 ;# SDCONF1
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mww 0xb0001010 0x0000015b ;# SDTIME0
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mww 0xb0001014 0x0000015b ;# SDTIME1
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mww 0xb0001018 0x00000000 ;# EXT0CON
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mww 0xb000101C 0x00000000 ;# EXT1CON
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mww 0xb0001020 0x00000000 ;# EXT2CON
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mww 0xb0001024 0x00000000 ;# EXT3CON
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mww 0xb000102c 0x00ff0048 ;# CKSKEW
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}
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