mirror of
https://git.code.sf.net/p/openocd/code
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4157732bd8
For historical reasons, no license information was added to the
tcl files. This makes trivial adding the SPDX tag through script:
fgrep -rL SPDX tcl/board | while read a;do \
sed -i '1{i# SPDX-License-Identifier: GPL-2.0-or-later\n
}' $a;done
With no specific license information from the author, let's extend
the OpenOCD project license GPL-2.0-or-later to the files.
Change-Id: Ibcf7da62e842aafd036a78db9ea2b9f11f79af16
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7028
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
85 lines
3.4 KiB
INI
85 lines
3.4 KiB
INI
# SPDX-License-Identifier: GPL-2.0-or-later
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## Chip:
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set CHIPNAME at91sam9260
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set CPUTAPID 0x0792603f
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set ENDIAN little
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source [find target/at91sam9260.cfg]
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$_TARGETNAME configure -event reset-init {at91sam_init}
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proc at91sam_init { } {
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# at reset chip runs at 32 kHz => 1/8 * 32 kHz = 4 kHz
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jtag_rclk 4
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# Enable user reset and disable watchdog
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mww 0xfffffd08 0xa5000501 ;# RSTC_MR : enable user reset
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mww 0xfffffd44 0x00008000 ;# WDT_MR : disable watchdog
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# Oscillator setup
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mww 0xfffffc20 0x00004001 ;# CKGR_MOR : enable the main oscillator (18.432 MHz)
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sleep 20 ;# wait 20 ms
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mww 0xfffffc30 0x00000001 ;# PMC_MCKR : switch to main oscillator
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sleep 10 ;# wait 10 ms
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# now we are running at 18.432 MHz kHz => 1/8 * 18.432 MHz = 2.304 MHz
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jtag_rclk 2000
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mww 0xfffffc28 0x2060bf09 ;# CKGR_PLLAR: Set PLLA Register for 198,656MHz
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sleep 20 ;# wait 20 ms
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mww 0xfffffc2c 0x207c3f0c ;# CKGR_PLLBR: Set PLLB Register for USB usage (USB_CLK = 48 MHz)
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sleep 10 ;# wait 10 ms
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mww 0xfffffc30 0x00000101 ;# PMC_MCKR : Select prescaler
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sleep 10 ;# wait 10 ms
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mww 0xfffffc30 0x00000102 ;# PMC_MCKR : Clock from PLLA is selected
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sleep 10 ;# wait 10 ms
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# now we are running at 198.656 MHz kHz => full speed jtag
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jtag_rclk 30000
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arm7_9 dcc_downloads enable ;# Enable faster DCC downloads
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# Configure PIO Controller for SDRAM data-lines D16-D31
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# PC16-PC31 = Peripheral A: D16-D32
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mww 0xfffff844 0xffff0000 ;# Interrupt Disable
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mww 0xfffff854 0xffff0000 ;# Multi-Drive Disable
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mww 0xfffff860 0xffff0000 ;# Pull-Up Disable
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mww 0xfffff870 0xffff0000 ;# PIO_ASR : Select peripheral A function for D15..D31
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mww 0xfffff804 0xffff0000 ;# PIO_PDR : Disable PIO function for D15..D31 (Peripheral function enable)
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mww 0xfffffc10 0x00000010 ;# Enable PIO-C Clock in PMC (PID=4)
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# SD-Ram setup
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mww 0xffffef1c 0x2 ;# EBI_CSA : Assign EBI Chip Select 1 to SDRAM
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mww 0xffffea08 0x85227259 ;# SDRAMC_CR : Configure SDRAM (IS42S32160A: 4M Words x 32 Bits x 4 Banks (512-Mbit))
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mww 0xffffea00 0x1 ;# SDRAMC_MR : issue a NOP command
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mww 0x20000000 0
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mww 0xffffea00 0x2 ;# SDRAMC_MR : issue an 'All Banks Precharge' command
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mww 0x20000000 0
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mww 0xffffea00 0x4 ;# SDRAMC_MR : issue an 'Auto-Refresh' command (1st)
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mww 0x20000000 0
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mww 0xffffea00 0x4 ;# SDRAMC_MR : issue an 'Auto-Refresh' command (2nd)
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mww 0x20000000 0
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mww 0xffffea00 0x4 ;# SDRAMC_MR : issue an 'Auto-Refresh' command (3th)
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mww 0x20000000 0
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mww 0xffffea00 0x4 ;# SDRAMC_MR : issue an 'Auto-Refresh' command (4th)
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mww 0x20000000 0
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mww 0xffffea00 0x4 ;# SDRAMC_MR : issue an 'Auto-Refresh' command (5th)
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mww 0x20000000 0
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mww 0xffffea00 0x4 ;# SDRAMC_MR : issue an 'Auto-Refresh' command (6th)
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mww 0x20000000 0
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mww 0xffffea00 0x4 ;# SDRAMC_MR : issue an 'Auto-Refresh' command (7th)
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mww 0x20000000 0
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mww 0xffffea00 0x4 ;# SDRAMC_MR : issue an 'Auto-Refresh' command (8th)
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mww 0x20000000 0
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mww 0xffffea00 0x3 ;# SDRAMC_MR : issue a 'Load Mode Register' command
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mww 0x20000000 0
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mww 0xffffea00 0x0 ;# SDRAMC_MR : Normal Mode
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mww 0x20000000 0
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mww 0xFFFFEA04 0x30d ;# SDRAM Refresh Time Register
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# datasheet: 8k refresh cycles / 64 ms
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# MCLK / (8*1024 / 64e-3) = 100e6 / 128000 = 781 = 0x30d
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}
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