mirror of
https://git.code.sf.net/p/openocd/code
synced 2024-11-22 03:46:27 +00:00
4157732bd8
For historical reasons, no license information was added to the
tcl files. This makes trivial adding the SPDX tag through script:
fgrep -rL SPDX tcl/board | while read a;do \
sed -i '1{i# SPDX-License-Identifier: GPL-2.0-or-later\n
}' $a;done
With no specific license information from the author, let's extend
the OpenOCD project license GPL-2.0-or-later to the files.
Change-Id: Ibcf7da62e842aafd036a78db9ea2b9f11f79af16
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7028
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
78 lines
1.9 KiB
INI
78 lines
1.9 KiB
INI
# SPDX-License-Identifier: GPL-2.0-or-later
|
|
|
|
# Keil MCB1700 PCB with 1768
|
|
#
|
|
# Reset init script sets it to 100MHz
|
|
set CCLK 100000
|
|
|
|
source [find target/lpc17xx.cfg]
|
|
|
|
global MCB1700_CCLK
|
|
set MCB1700_CCLK $CCLK
|
|
|
|
$_TARGETNAME configure -event reset-start {
|
|
# Start *real slow* as we do not know the
|
|
# state the boot rom left the clock in
|
|
adapter speed 10
|
|
}
|
|
|
|
# Set up 100MHz clock to CPU
|
|
$_TARGETNAME configure -event reset-init {
|
|
# PLL0CON: Disable PLL
|
|
mww 0x400FC080 0x00000000
|
|
# PLLFEED
|
|
mww 0x400FC08C 0x000000AA
|
|
# PLLFEED
|
|
mww 0x400FC08C 0x00000055
|
|
|
|
# CCLK=PLL/4 (=100 MHz)
|
|
mww 0x400FC104 0x00000003
|
|
# CLKSRCSEL: Clock source = internal RC oscillator
|
|
mww 0x400FC10C 0x00000000
|
|
|
|
# PLL0CFG: M=50,N=1 -> PLL=400 MHz
|
|
mww 0x400FC084 0x00000031
|
|
# PLLFEED
|
|
mww 0x400FC08C 0x000000AA
|
|
# PLLFEED
|
|
mww 0x400FC08C 0x00000055
|
|
|
|
# PLL0CON: Enable PLL
|
|
mww 0x400FC080 0x00000001
|
|
# PLLFEED
|
|
mww 0x400FC08C 0x000000AA
|
|
# PLLFEED
|
|
mww 0x400FC08C 0x00000055
|
|
|
|
sleep 50
|
|
|
|
# PLL0CON: Connect PLL
|
|
mww 0x400FC080 0x00000003
|
|
# PLLFEED
|
|
mww 0x400FC08C 0x000000AA
|
|
# PLLFEED
|
|
mww 0x400FC08C 0x00000055
|
|
|
|
# Dividing CPU clock by 8 should be pretty conservative
|
|
#
|
|
#
|
|
global MCB1700_CCLK
|
|
adapter speed [expr {$MCB1700_CCLK / 8}]
|
|
|
|
# Do not remap 0x0000-0x0020 to anything but the flash (i.e. select
|
|
# "User Flash Mode" where interrupt vectors are _not_ remapped,
|
|
# and reside in flash instead).
|
|
#
|
|
# See Table 612. Memory Mapping Control register (MEMMAP - 0x400F C040) bit description
|
|
# Bit Symbol Value Description Reset
|
|
# value
|
|
# 0 MAP Memory map control. 0
|
|
# 0 Boot mode. A portion of the Boot ROM is mapped to address 0.
|
|
# 1 User mode. The on-chip Flash memory is mapped to address 0.
|
|
# 31:1 - Reserved. The value read from a reserved bit is not defined. NA
|
|
#
|
|
# http://ics.nxp.com/support/documents/microcontrollers/?scope=LPC1768&type=user
|
|
|
|
mww 0x400FC040 0x01
|
|
}
|