mirror of
https://git.code.sf.net/p/openocd/code
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4157732bd8
For historical reasons, no license information was added to the
tcl files. This makes trivial adding the SPDX tag through script:
fgrep -rL SPDX tcl/board | while read a;do \
sed -i '1{i# SPDX-License-Identifier: GPL-2.0-or-later\n
}' $a;done
With no specific license information from the author, let's extend
the OpenOCD project license GPL-2.0-or-later to the files.
Change-Id: Ibcf7da62e842aafd036a78db9ea2b9f11f79af16
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7028
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
115 lines
2.7 KiB
INI
115 lines
2.7 KiB
INI
# SPDX-License-Identifier: GPL-2.0-or-later
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# Intel "Lubbock" Development Board with PXA255 (dbpxa255)
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# Obsolete; this was Intel's original PXA255 development system
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# Board also had CPU cards for SA1100, PXA210, PXA250, and more.
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source [find target/pxa255.cfg]
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adapter srst delay 250
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jtag_ntrst_delay 250
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# NOTE: until after pinmux and such are set up, only CS0 is
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# available ... not 2nd bank of CFI, or FPGA, SRAM, ENET, etc.
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# CS0, CS1 -- two banks of CFI flash, 32 MBytes each
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# each bank is 32-bits wide, two 16-bit chips in parallel
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set _FLASHNAME $_CHIPNAME.flash0
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flash bank $_FLASHNAME cfi 0x00000000 0x02000000 2 4 $_TARGETNAME
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set _FLASHNAME $_CHIPNAME.flash1
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flash bank $_FLASHNAME cfi 0x04000000 0x02000000 2 4 $_TARGETNAME
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# CS2 low -- FPGA registers
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# CS2 high -- 1 MByte SRAM at 0x0a00.0000 ... last 64K for scratch
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$_TARGETNAME configure -work-area-phys 0x0a0f0000
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$_TARGETNAME configure -event reset-assert-pre \
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"$_TARGETNAME configure -work-area-size 0"
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# Make the hex led display a number, assuming CS2 is set up
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# and all digits have been enabled through the FPGA.
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proc hexled {u32} {
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mww 0x08000010 $u32
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}
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# CS3 -- Ethernet
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# CS4 -- SA1111
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# CS5 -- PCMCIA
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# NOTE: system console normally uses the FF UART connector
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proc lubbock_init {target} {
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echo "Initialize PXA255 Lubbock board"
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# (1) pinmux
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# GPSR0..GPSR2
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mww 0x40e00018 0x00008000
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mww 0x40e0001c 0x00FC0382
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mww 0x40e00020 0x0001FFFF
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# GPDR0..GPDR2
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mww 0x40e0000c 0x0060A800
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mww 0x40e00010 0x00FF0382
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mww 0x40e00014 0x0001C000
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# GAFR0_[LU]..GAFR2_[LU]
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mww 0x40e00054 0x98400000
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mww 0x40e00058 0x00002950
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mww 0x40e0005c 0x000A9558
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mww 0x40e00060 0x0005AAAA
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mww 0x40e00064 0xA0000000
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mww 0x40e00068 0x00000002
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# write PSSR, enable GPIOs
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mww 0x40f00000 0x00000020
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# write LED ctrl register ... ones disable
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# high byte, 8 hex leds; low byte, 8 discretes
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mwh 0x08000040 0xf0ff
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hexled 0x0000
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# (2) Address space setup
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# MSC0/MSC1/MSC2
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mww 0x48000008 0x23f223f2
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mww 0x4800000c 0x3ff1a441
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mww 0x48000010 0x7ff97ff1
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# pcmcia/cf
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mww 0x48000014 0x00000000
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mww 0x48000028 0x00010504
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mww 0x4800002c 0x00010504
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mww 0x48000030 0x00010504
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mww 0x48000034 0x00010504
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mww 0x48000038 0x00004715
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mww 0x4800003c 0x00004715
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hexled 0x1111
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# (3) SDRAM setup
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# REVISIT this looks dubious ... no refresh cycles
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mww 0x48000004 0x03CA4018
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mww 0x48000004 0x004B4018
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mww 0x48000004 0x000B4018
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mww 0x48000004 0x000BC018
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mww 0x48000000 0x00001AC8
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mww 0x48000000 0x00001AC9
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mww 0x48000040 0x00000000
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# FIXME -- setup:
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# CLOCKS (and faster JTAG)
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# enable icache
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# FIXME SRAM isn't working
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# $target configure -work-area-size 0x10000
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hexled 0x2222
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flash probe 0
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flash probe 1
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hexled 0xcafe
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}
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$_TARGETNAME configure -event reset-init "lubbock_init $_TARGETNAME"
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