mirror of
https://git.code.sf.net/p/openocd/code
synced 2024-11-22 04:56:28 +00:00
4157732bd8
For historical reasons, no license information was added to the
tcl files. This makes trivial adding the SPDX tag through script:
fgrep -rL SPDX tcl/board | while read a;do \
sed -i '1{i# SPDX-License-Identifier: GPL-2.0-or-later\n
}' $a;done
With no specific license information from the author, let's extend
the OpenOCD project license GPL-2.0-or-later to the files.
Change-Id: Ibcf7da62e842aafd036a78db9ea2b9f11f79af16
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7028
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
255 lines
6.5 KiB
INI
255 lines
6.5 KiB
INI
# SPDX-License-Identifier: GPL-2.0-or-later
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# The IMX35PDK eval board has a single IMX35 chip
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source [find target/imx35.cfg]
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source [find target/imx.cfg]
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$_TARGETNAME configure -event reset-init { imx35pdk_init }
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# Stick to *really* low clock rate or reset will fail
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# without RTCK / RCLK
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jtag_rclk 10
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proc imx35pdk_init { } {
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imx3x_reset
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mww 0x43f00040 0x00000000
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mww 0x43f00044 0x00000000
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mww 0x43f00048 0x00000000
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mww 0x43f0004C 0x00000000
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mww 0x43f00050 0x00000000
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mww 0x43f00000 0x77777777
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mww 0x43f00004 0x77777777
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mww 0x53f00040 0x00000000
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mww 0x53f00044 0x00000000
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mww 0x53f00048 0x00000000
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mww 0x53f0004C 0x00000000
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mww 0x53f00050 0x00000000
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mww 0x53f00000 0x77777777
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mww 0x53f00004 0x77777777
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# clock setup
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mww 0x53F80004 0x00821000 ;# first need to set IPU_HND_BYP
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mww 0x53F80004 0x00821000 ;#arm clock is 399Mhz and ahb clock is 133Mhz.
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#=================================================
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# WEIM config
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#=================================================
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# CS0U
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mww 0xB8002000 0x0000CC03
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# CS0L
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mww 0xB8002004 0xA0330D01
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# CS0A
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mww 0xB8002008 0x00220800
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# CS5U
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mww 0xB8002050 0x0000dcf6
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# CS5L
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mww 0xB8002054 0x444a4541
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# CS5A
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mww 0xB8002058 0x44443302
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# IO SW PAD Control registers - setting of 0x0002 is high drive, mDDR
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mww 0x43FAC368 0x00000006
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mww 0x43FAC36C 0x00000006
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mww 0x43FAC370 0x00000006
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mww 0x43FAC374 0x00000006
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mww 0x43FAC378 0x00000006
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mww 0x43FAC37C 0x00000006
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mww 0x43FAC380 0x00000006
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mww 0x43FAC384 0x00000006
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mww 0x43FAC388 0x00000006
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mww 0x43FAC38C 0x00000006
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mww 0x43FAC390 0x00000006
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mww 0x43FAC394 0x00000006
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mww 0x43FAC398 0x00000006
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mww 0x43FAC39C 0x00000006
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mww 0x43FAC3A0 0x00000006
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mww 0x43FAC3A4 0x00000006
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mww 0x43FAC3A8 0x00000006
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mww 0x43FAC3AC 0x00000006
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mww 0x43FAC3B0 0x00000006
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mww 0x43FAC3B4 0x00000006
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mww 0x43FAC3B8 0x00000006
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mww 0x43FAC3BC 0x00000006
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mww 0x43FAC3C0 0x00000006
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mww 0x43FAC3C4 0x00000006
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mww 0x43FAC3C8 0x00000006
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mww 0x43FAC3CC 0x00000006
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mww 0x43FAC3D0 0x00000006
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mww 0x43FAC3D4 0x00000006
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mww 0x43FAC3D8 0x00000006
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# DDR data bus SD 0 through 31
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mww 0x43FAC3DC 0x00000082
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mww 0x43FAC3E0 0x00000082
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mww 0x43FAC3E4 0x00000082
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mww 0x43FAC3E8 0x00000082
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mww 0x43FAC3EC 0x00000082
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mww 0x43FAC3F0 0x00000082
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mww 0x43FAC3F4 0x00000082
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mww 0x43FAC3F8 0x00000082
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mww 0x43FAC3FC 0x00000082
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mww 0x43FAC400 0x00000082
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mww 0x43FAC404 0x00000082
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mww 0x43FAC408 0x00000082
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mww 0x43FAC40C 0x00000082
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mww 0x43FAC410 0x00000082
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mww 0x43FAC414 0x00000082
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mww 0x43FAC418 0x00000082
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mww 0x43FAC41c 0x00000082
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mww 0x43FAC420 0x00000082
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mww 0x43FAC424 0x00000082
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mww 0x43FAC428 0x00000082
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mww 0x43FAC42c 0x00000082
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mww 0x43FAC430 0x00000082
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mww 0x43FAC434 0x00000082
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mww 0x43FAC438 0x00000082
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mww 0x43FAC43c 0x00000082
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mww 0x43FAC440 0x00000082
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mww 0x43FAC444 0x00000082
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mww 0x43FAC448 0x00000082
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mww 0x43FAC44c 0x00000082
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mww 0x43FAC450 0x00000082
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mww 0x43FAC454 0x00000082
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mww 0x43FAC458 0x00000082
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# DQM setup
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mww 0x43FAC45c 0x00000082
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mww 0x43FAC460 0x00000082
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mww 0x43FAC464 0x00000082
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mww 0x43FAC468 0x00000082
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mww 0x43FAC46c 0x00000006
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mww 0x43FAC470 0x00000006
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mww 0x43FAC474 0x00000006
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mww 0x43FAC478 0x00000006
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mww 0x43FAC47c 0x00000006
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mww 0x43FAC480 0x00000006 ;# CSD0
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mww 0x43FAC484 0x00000006 ;# CSD1
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mww 0x43FAC488 0x00000006
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mww 0x43FAC48c 0x00000006
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mww 0x43FAC490 0x00000006
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mww 0x43FAC494 0x00000006
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mww 0x43FAC498 0x00000006
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mww 0x43FAC49c 0x00000006
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mww 0x43FAC4A0 0x00000006
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mww 0x43FAC4A4 0x00000006 ;# RAS
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mww 0x43FAC4A8 0x00000006 ;# CAS
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mww 0x43FAC4Ac 0x00000006 ;# SDWE
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mww 0x43FAC4B0 0x00000006 ;# SDCKE0
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mww 0x43FAC4B4 0x00000006 ;# SDCKE1
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mww 0x43FAC4B8 0x00000002 ;# SDCLK
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# SDQS0 through SDQS3
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mww 0x43FAC4Bc 0x00000082
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mww 0x43FAC4C0 0x00000082
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mww 0x43FAC4C4 0x00000082
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mww 0x43FAC4C8 0x00000082
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# *==================================================
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# Initialization script for 32 bit DDR2 on RINGO 3DS
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# *==================================================
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#--------------------------------------------
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# Init CCM
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#--------------------------------------------
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mww 0x53F80028 0x7D000028
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#--------------------------------------------
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# Init IOMUX for JTAG
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#--------------------------------------------
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mww 0x43FAC5EC 0x000000C3
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mww 0x43FAC5F0 0x000000C3
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mww 0x43FAC5F4 0x000000F3
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mww 0x43FAC5F8 0x000000F3
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mww 0x43FAC5FC 0x000000F3
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mww 0x43FAC600 0x000000F3
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mww 0x43FAC604 0x000000F3
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# ESD_MISC : enable DDR2
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mww 0xB8001010 0x00000304
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#--------------------------------------------
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# Init 32-bit DDR2 memory on CSD0
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# COL=10-bit, ROW=13-bit, BA[1:0]=Addr[26:25]
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#--------------------------------------------
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# ESD_ESDCFG0 : set timing parameters
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mww 0xB8001004 0x007ffC2f
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# ESD_ESDCTL0 : select Prechare-All mode
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mww 0xB8001000 0x92220000
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# DDR2 : Prechare-All
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mww 0x80000400 0x12345678
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# ESD_ESDCTL0 : select Load-Mode-Register mode
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mww 0xB8001000 0xB2220000
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# DDR2 : Load reg EMR2
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mwb 0x84000000 0xda
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# DDR2 : Load reg EMR3
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mwb 0x86000000 0xda
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# DDR2 : Load reg EMR1 -- enable DLL
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mwb 0x82000400 0xda
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# DDR2 : Load reg MR -- reset DLL
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mwb 0x80000333 0xda
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# ESD_ESDCTL0 : select Prechare-All mode
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mww 0xB8001000 0x92220000
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# DDR2 : Prechare-All
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mwb 0x80000400 0x12345678
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# ESD_ESDCTL0 : select Manual-Refresh mode
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mww 0xB8001000 0xA2220000
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# DDR2 : Manual-Refresh 2 times
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mww 0x80000000 0x87654321
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mww 0x80000000 0x87654321
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# ESD_ESDCTL0 : select Load-Mode-Register mode
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mww 0xB8001000 0xB2220000
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# DDR2 : Load reg MR -- CL=3, BL=8, end DLL reset
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mwb 0x80000233 0xda
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# DDR2 : Load reg EMR1 -- OCD default
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mwb 0x82000780 0xda
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# DDR2 : Load reg EMR1 -- OCD exit
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mwb 0x82000400 0xda ;# ODT disabled
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# ESD_ESDCTL0 : select normal-operation mode
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# DSIZ=32-bit, BL=8, COL=10-bit, ROW=13-bit
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# disable PWT & PRCT
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# disable Auto-Refresh
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mww 0xB8001000 0x82220080
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## ESD_ESDCTL0 : enable Auto-Refresh
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mww 0xB8001000 0x82228080
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## ESD_ESDCTL1 : enable Auto-Refresh
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mww 0xB8001008 0x00002000
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#***********************************************
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# Adjust the ESDCDLY5 register
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#***********************************************
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# Vary DQS_ABS_OFFSET5 for writes
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mww 0xB8001020 0x00F48000 ;# this is the default value
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mww 0xB8001024 0x00F48000 ;# this is the default value
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mww 0xB8001028 0x00F48000 ;# this is the default value
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mww 0xB800102c 0x00F48000 ;# this is the default value
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#Then you can make force measure with the dedicated bit (Bit 7 at ESDMISC)
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mww 0xB8001010 0x00000384
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# wait a while
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sleep 1000
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# now clear the force measurement bit
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mww 0xB8001010 0x00000304
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# dummy write to DDR memory to set DQS low
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mww 0x80000000 0x00000000
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mww 0x30000100 0x0
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mww 0x30000104 0x31024
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}
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