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https://git.code.sf.net/p/openocd/code
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4157732bd8
For historical reasons, no license information was added to the
tcl files. This makes trivial adding the SPDX tag through script:
fgrep -rL SPDX tcl/board | while read a;do \
sed -i '1{i# SPDX-License-Identifier: GPL-2.0-or-later\n
}' $a;done
With no specific license information from the author, let's extend
the OpenOCD project license GPL-2.0-or-later to the files.
Change-Id: Ibcf7da62e842aafd036a78db9ea2b9f11f79af16
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7028
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
79 lines
1.9 KiB
INI
79 lines
1.9 KiB
INI
# SPDX-License-Identifier: GPL-2.0-or-later
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# The IMX27 ADS eval board has a single IMX27 chip
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# Note: tested on IMX27ADS Board REV-2.6 and REV-2.8
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source [find target/imx27.cfg]
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$_TARGETNAME configure -event gdb-attach { reset init }
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$_TARGETNAME configure -event reset-init { imx27ads_init }
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# The IMX27 ADS board has a NOR flash on CS0
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set _FLASHNAME $_CHIPNAME.flash
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flash bank $_FLASHNAME cfi 0xc0000000 0x00200000 2 2 $_TARGETNAME
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proc imx27ads_init { } {
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# This setup puts RAM at 0xA0000000
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# reset the board correctly
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reset run
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reset halt
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mww 0x10000000 0x20040304
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mww 0x10020000 0x00000000
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mww 0x10000004 0xDFFBFCFB
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mww 0x10020004 0xFFFFFFFF
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sleep 100
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# ========================================
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# Configure DDR on CSD0 -- initial reset
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# ========================================
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mww 0xD8001010 0x00000008
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# ========================================
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# Configure PSRAM on CS5
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# ========================================
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mww 0xd8002050 0x0000dcf6
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mww 0xd8002054 0x444a4541
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mww 0xd8002058 0x44443302
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# ========================================
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# Configure16 bit NorFlash on CS0
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# ========================================
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mww 0xd8002000 0x0000CC03
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mww 0xd8002004 0xa0330D01
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mww 0xd8002008 0x00220800
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# ========================================
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# Configure CPLD on CS4
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# ========================================
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mww 0xd8002040 0x0000DCF6
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mww 0xd8002044 0x444A4541
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mww 0xd8002048 0x44443302
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# ========================================
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# Configure DDR on CSD0 -- wait 5000 cycle
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# ========================================
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mww 0x10027828 0x55555555
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mww 0x10027830 0x55555555
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mww 0x10027834 0x55555555
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mww 0x10027838 0x00005005
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mww 0x1002783C 0x15555555
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mww 0xD8001010 0x00000004
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mww 0xD8001004 0x00795729
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mww 0xD8001000 0x92200000
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mww 0xA0000F00 0x0
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mww 0xD8001000 0xA2200000
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mww 0xA0000F00 0x0
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mww 0xA0000F00 0x0
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mww 0xD8001000 0xB2200000
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mwb 0xA0000033 0xFF
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mwb 0xA1000000 0xAA
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mww 0xD8001000 0x82228085
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}
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