mirror of
https://git.code.sf.net/p/openocd/code
synced 2024-11-22 03:46:27 +00:00
4157732bd8
For historical reasons, no license information was added to the
tcl files. This makes trivial adding the SPDX tag through script:
fgrep -rL SPDX tcl/board | while read a;do \
sed -i '1{i# SPDX-License-Identifier: GPL-2.0-or-later\n
}' $a;done
With no specific license information from the author, let's extend
the OpenOCD project license GPL-2.0-or-later to the files.
Change-Id: Ibcf7da62e842aafd036a78db9ea2b9f11f79af16
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7028
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
154 lines
6.1 KiB
INI
154 lines
6.1 KiB
INI
# SPDX-License-Identifier: GPL-2.0-or-later
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# Embedded Artists eval board for LPC2478
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# http://www.embeddedartists.com/
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# Target device: LPC2478
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set CCLK 72000
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source [find target/lpc2478.cfg]
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# Helper
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#
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proc read_register {register} {
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return [read_memory $register 32 1]
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}
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proc init_board {} {
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# Delays on reset lines
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adapter srst delay 500
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jtag_ntrst_delay 1
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# Adaptive JTAG clocking through RTCK.
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#
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jtag_rclk 20
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global _TARGETNAME
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global _CHIPNAME
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# A working area will help speeding the flash programming
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$_TARGETNAME configure -work-area-phys 0x40000200 -work-area-size [expr {0x10000-0x200-0x20}] -work-area-backup 0
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# External 16-bit flash at chip select CS0 (SST39VF3201-70, 4 MiB)
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flash bank $_CHIPNAME.extflash cfi 0x80000000 0x400000 2 2 $_TARGETNAME jedec_probe
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# Event handlers
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#
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$_TARGETNAME configure -event reset-start {
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# Back to the slow JTAG clock
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jtag_rclk 20
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}
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$_TARGETNAME configure -event reset-init {
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arm core_state arm
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arm7_9 dcc_downloads enable ;# Speed up downloads by using DCC transfer
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arm7_9 fast_memory_access enable
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# Peripheral clocks
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mww 0xE01FC0C4 0x04280FFE ;# PCONP: (reset value)
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# Map the user flash to the vector table area (0x00...0x3F)
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mww 0xE01FC040 0x00000001 ;# MEMMAP: User flash
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# Memory accelerator module
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mww 0xE01FC004 0x00000003 ;# MAMTIM: 3 clock cycles
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mww 0xE01FC000 0x00000002 ;# MAMCR: fully enabled
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# Enable external memory bus (32-bit SDRAM at DYCS0, 16-bit flash at CS0)
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mww 0xE002C014 0x55010115 ;# PINSEL5: P2.16=CAS, P2.17=RAS, P2.18=CLKOUT0,
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# P2.20=DYCS0, P2.24=CKEOUT0, P2.28=DQMOUT0,
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# P2.29=DQMOUT1, P2.30=DQMOUT2, P2.31=DQMOUT3
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mww 0xE002C018 0x55555555 ;# PINSEL6: P3.0...P3.15=D0...D15
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mww 0xE002C01C 0x55555555 ;# PINSEL7: P3.16...P3.31=D16...D31
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mww 0xE002C020 0x55555555 ;# PINSEL8: P4.0...P4.15=A0...A15
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mww 0xE002C024 0x50051555 ;# PINSEL9: P4.16...P4.22=A16...A22, P4.24=OE,
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# P4.25=WE, P4.30=CS0, P4.31=CS1
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mww 0xFFE08000 0x00000001 ;# EMCControl: Enable EMC
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# Start PLL, then use faster JTAG clock
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enable_pll
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jtag_rclk 3000
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# 16-bit flash @ CS0 (SST39VF3201-70)
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mww 0xFFE08200 0x00080081 ;# EMCStaticConfig0: 16 bit, PB=1, buffers on
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mww 0xFFE08204 0x00000000 ;# EMCStaticWaitWen0
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mww 0xFFE08208 0x00000000 ;# EMCStaticWaitOen0
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mww 0xFFE0820C 0x00000005 ;# EMCStaticWaitRd0
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mww 0xFFE08210 0x00000005 ;# EMCStaticWaitPage0
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mww 0xFFE08214 0x00000003 ;# EMCStaticWaitWr0
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mww 0xFFE08218 0x00000001 ;# EMCStaticWaitTurn0
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# 8-bit NAND @ CS1
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# TODO
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# 32-bit SDRAM @ DYCS0 (K4M563233G-HN75)
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mww 0xFFE08028 0x00000001 ;# EMCDynamicReadConfig
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mww 0xFFE08030 0x00000001 ;# EMCDynamicRP
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mww 0xFFE08034 0x00000003 ;# EMCDynamicRAS
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mww 0xFFE08038 0x00000005 ;# EMCDynamicSREX
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mww 0xFFE0803C 0x00000001 ;# EMCDynamicAPR
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mww 0xFFE08040 0x00000005 ;# EMCDynamicDAL
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mww 0xFFE08044 0x00000001 ;# EMCDynamicWR
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mww 0xFFE08048 0x00000005 ;# EMCDynamicRC
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mww 0xFFE0804C 0x00000005 ;# EMCDynamicRFC
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mww 0xFFE08050 0x00000005 ;# EMCDynamicXSR
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mww 0xFFE08054 0x00000001 ;# EMCDynamicRRD
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mww 0xFFE08058 0x00000001 ;# EMCDynamicMRD
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#
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mww 0xFFE08104 0x00000202 ;# EMCDynamicRasCas0
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mww 0xFFE08100 0x00005488 ;# EMCDynamicConfig0
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sleep 100
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mww 0xFFE08020 0x00000183 ;# EMCDynamicControl: Clock on continuously, NOP
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sleep 10
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mww 0xFFE08020 0x00000103 ;# EMCDynamicControl: PRECHARGE-ALL
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mww 0xFFE08024 0x00000046 ;# EMCDynamicRefresh
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sleep 100
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mww 0xFFE08020 0x00000083 ;# EMCDynamicControl: MODE
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mdw 0xA0011000 1 ;# Set SDRAM mode register
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mww 0xFFE08020 0x00000000 ;# EMCDynamicControl: NORMAL
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mww 0xFFE08100 0x00085488 ;# EMCDynamicConfig0: Enable buffers
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}
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$_TARGETNAME configure -event gdb-attach {
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# Without this gdb-attach will first time as probe will fail
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reset init
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}
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}
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# Enable the PLL.
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# Generate maximum CPU clock (72 MHz) Run from internal RC oscillator.
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# Note: The PLL output runs at a frequency N times the desired CPU clock.
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# It in unavoidable that the CPU clock drops down to (4 MHz/N) during
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# the initialization!
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# Here: N=4
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# Note that if the PLL is already active at the time this script is
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# called, the effective value of N is the value of CCLKCFG at that time!
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#
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proc enable_pll {} {
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# Disconnect PLL in case it is already connected
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if {[expr {[read_register 0xE01FC080] & 0x03}] == 3} {
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# Disconnect it, but leave it enabled
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# (This MUST be done in two steps)
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mww 0xE01FC080 0x00000001 ;# PLLCON: disconnect PLL
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mww 0xE01FC08C 0x000000AA ;# PLLFEED
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mww 0xE01FC08C 0x00000055 ;# PLLFEED
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}
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# Disable PLL (as it might already be enabled at this time!)
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mww 0xE01FC080 0x00000000 ;# PLLCON: disable PLL
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mww 0xE01FC08C 0x000000AA ;# PLLFEED
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mww 0xE01FC08C 0x00000055 ;# PLLFEED
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# Setup PLL to generate 288 MHz from internal RC oscillator
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mww 0xE01FC10C 0x00000000 ;# CLKSRCSEL: IRC
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mww 0xE01FC084 0x00000023 ;# PLLCFG: N=1, M=36
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mww 0xE01FC08C 0x000000AA ;# PLLFEED
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mww 0xE01FC08C 0x00000055 ;# PLLFEED
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mww 0xE01FC080 0x00000001 ;# PLLCON: enable PLL
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mww 0xE01FC08C 0x000000AA ;# PLLFEED
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mww 0xE01FC08C 0x00000055 ;# PLLFEED
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sleep 100
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mww 0xE01FC104 0x00000003 ;# CCLKCFG: divide by 4 (72 MHz)
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mww 0xE01FC080 0x00000003 ;# PLLCON: connect PLL
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mww 0xE01FC08C 0x000000AA ;# PLLFEED
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mww 0xE01FC08C 0x00000055 ;# PLLFEED
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}
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