mirror of
https://git.code.sf.net/p/openocd/code
synced 2024-11-22 04:56:28 +00:00
4157732bd8
For historical reasons, no license information was added to the
tcl files. This makes trivial adding the SPDX tag through script:
fgrep -rL SPDX tcl/board | while read a;do \
sed -i '1{i# SPDX-License-Identifier: GPL-2.0-or-later\n
}' $a;done
With no specific license information from the author, let's extend
the OpenOCD project license GPL-2.0-or-later to the files.
Change-Id: Ibcf7da62e842aafd036a78db9ea2b9f11f79af16
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7028
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
96 lines
2.3 KiB
INI
96 lines
2.3 KiB
INI
# SPDX-License-Identifier: GPL-2.0-or-later
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# Elector Internet Radio board
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# http://www.ethernut.de/en/hardware/eir/index.html
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source [find target/at91sam7se512.cfg]
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$_TARGETNAME configure -event reset-init {
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# WDT_MR, disable watchdog
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mww 0xFFFFFD44 0x00008000
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# RSTC_MR, enable user reset
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mww 0xfffffd08 0xa5000001
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# CKGR_MOR
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mww 0xFFFFFC20 0x00000601
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sleep 10
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# CKGR_PLLR
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mww 0xFFFFFC2C 0x00481c0e
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sleep 10
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# PMC_MCKR
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mww 0xFFFFFC30 0x00000007
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sleep 10
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# PMC_IER
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mww 0xFFFFFF60 0x00480100
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#
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# Enable SDRAM interface.
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#
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# Enable SDRAM control at PIO A.
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mww 0xfffff474 0x3f800000 ;# PIO_BSR_OFF
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mww 0xfffff404 0x3f800000 ;# PIO_PDR_OFF
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# Enable address bus (A0, A2-A11, A13-A17) at PIO B
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mww 0xfffff674 0x0003effd ;# PIO_BSR_OFF
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mww 0xfffff604 0x0003effd ;# PIO_PDR_OFF
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# Enable 16 bit data bus at PIO C
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mww 0xfffff870 0x0000ffff ;# PIO_ASR_OFF
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mww 0xfffff804 0x0000ffff ;# PIO_PDR_OFF
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# Enable SDRAM chip select
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mww 0xffffff80 0x00000002 ;# EBI_CSA_OFF
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# Set SDRAM characteristics in configuration register.
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# Hard coded values for MT48LC32M16A2 with 48MHz CPU.
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mww 0xffffffb8 0x2192215a ;# SDRAMC_CR_OFF
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sleep 10
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# Issue 16 bit SDRAM command: NOP
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mww 0xffffffb0 0x00000011 ;# SDRAMC_MR_OFF
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mww 0x20000000 0x00000000
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# Issue 16 bit SDRAM command: Precharge all
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mww 0xffffffb0 0x00000012 ;# SDRAMC_MR_OFF
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mww 0x20000000 0x00000000
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# Issue 8 auto-refresh cycles
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mww 0xffffffb0 0x00000014 ;# SDRAMC_MR_OFF
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mww 0x20000000 0x00000000
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mww 0xffffffb0 0x00000014 ;# SDRAMC_MR_OFF
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mww 0x20000000 0x00000000
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mww 0xffffffb0 0x00000014 ;# SDRAMC_MR_OFF
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mww 0x20000000 0x00000000
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mww 0xffffffb0 0x00000014 ;# SDRAMC_MR_OFF
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mww 0x20000000 0x00000000
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mww 0xffffffb0 0x00000014 ;# SDRAMC_MR_OFF
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mww 0x20000000 0x00000000
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mww 0xffffffb0 0x00000014 ;# SDRAMC_MR_OFF
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mww 0x20000000 0x00000000
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mww 0xffffffb0 0x00000014 ;# SDRAMC_MR_OFF
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mww 0x20000000 0x00000000
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mww 0xffffffb0 0x00000014 ;# SDRAMC_MR_OFF
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mww 0x20000000 0x00000000
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# Issue 16 bit SDRAM command: Set mode register
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mww 0xffffffb0 0x00000013 ;# SDRAMC_MR_OFF
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mww 0x20000014 0xcafedede
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# Set refresh rate count ???
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mww 0xffffffb4 0x00000013 ;# SDRAMC_TR_OFF
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# Issue 16 bit SDRAM command: Normal mode
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mww 0xffffffb0 0x00000010 ;# SDRAMC_MR_OFF
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mww 0x20000000 0x00000180
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#
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# Enable external reset key.
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#
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mww 0xfffffd08 0xa5000001
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}
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