mirror of
https://git.code.sf.net/p/openocd/code
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4157732bd8
For historical reasons, no license information was added to the
tcl files. This makes trivial adding the SPDX tag through script:
fgrep -rL SPDX tcl/board | while read a;do \
sed -i '1{i# SPDX-License-Identifier: GPL-2.0-or-later\n
}' $a;done
With no specific license information from the author, let's extend
the OpenOCD project license GPL-2.0-or-later to the files.
Change-Id: Ibcf7da62e842aafd036a78db9ea2b9f11f79af16
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7028
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
35 lines
960 B
INI
35 lines
960 B
INI
# SPDX-License-Identifier: GPL-2.0-or-later
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# Product page:
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# https://www.dptechnics.com/en/products/dpt-board-v1.html
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#
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# JTAG is a 5 pin array located close to main module in following order:
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# 1. JTAG TCK
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# 2. JTAG TDO
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# 3. JTAG TDI
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# 4. JTAG TMS
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# 5. GND The GND is located near letter G of word JTAG on board.
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#
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# Two RST pins are connected to:
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# 1. GND
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# 2. GPIO11 this pin is located near letter R of word RST.
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#
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# To enable EJTAG mode, GPIO11 (RST[1]) pin should be pulled up. For example
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# with 10K resistor connected to V3.3 pin.
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#
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# This board is powered from micro USB connector. No real reset pin or button, for
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# example RESET_L is available.
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source [find target/atheros_ar9331.cfg]
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$_TARGETNAME configure -event reset-init {
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ar9331_25mhz_pll_init
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sleep 1
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ar9331_ddr2_init
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}
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set ram_boot_address 0xa0000000
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$_TARGETNAME configure -work-area-phys 0xa1FFE000 -work-area-size 0x1000
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flash bank flash0 ath79 0xbf000000 0 0 0 $_TARGETNAME cs0
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