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75b418faa7
Support Digilent Anvyl board JTAG chain Change-Id: I6fb52284429af6c98c19411fc8bc3ab983dfa9b8 Signed-off-by: Adam Novak <interfect@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/8467 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
28 lines
713 B
INI
28 lines
713 B
INI
# SPDX-License-Identifier: GPL-2.0-or-later
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# Digilent Anvyl with Xilinx Spartan-6 FPGA
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# https://digilent.com/reference/programmable-logic/anvyl/start
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# Almost the same setup as the Digilent Nexys Video board or the Digilent HS1
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# adapter.
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adapter driver ftdi
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adapter speed 30000
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ftdi device_desc "Digilent USB Device"
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ftdi vid_pid 0x0403 0x6010
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# channel 0 is the JTAG channel
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# channel 1 is a user serial channel to pins on the FPGA
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ftdi channel 0
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# just TCK TDI TDO TMS, no reset
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ftdi layout_init 0x0088 0x008b
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reset_config none
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# Enable sampling on falling edge for high JTAG speeds.
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ftdi tdo_sample_edge falling
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transport select jtag
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source [find cpld/xilinx-xc6s.cfg]
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source [find cpld/jtagspi.cfg]
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